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| author | oharboe <oharboe> | 2008-04-22 05:52:16 +0000 |
|---|---|---|
| committer | oharboe <oharboe> | 2008-04-22 05:52:16 +0000 |
| commit | d09fa3de9df02a66c5084623076ac3e167b58274 (patch) | |
| tree | b734b58ae8ca60717464d503e9a9bcd4a98727a7 /zpu/hdl/zpu4/src/trace.vhd | |
| parent | 167263dcae188a8812627ab52cfd96b8fdc5df8a (diff) | |
| download | zpu-d09fa3de9df02a66c5084623076ac3e167b58274.zip zpu-d09fa3de9df02a66c5084623076ac3e167b58274.tar.gz | |
* zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh,
zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example
* zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL
* zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL
* zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL
* zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd,
zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd,
zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd,
zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd,
zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd,
zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd,
zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std
Diffstat (limited to 'zpu/hdl/zpu4/src/trace.vhd')
| -rw-r--r-- | zpu/hdl/zpu4/src/trace.vhd | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index bc5279f..e687aaf 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,7 +1,6 @@ library ieee;
use ieee.std_logic_1164.all;
---use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
use std.textio.all;
@@ -45,7 +44,7 @@ receive_data: process variable l: line;
variable t : std_logic_vector(wordSize-1 downto 0);
variable t2 : std_logic_vector(maxAddrBitIncIO downto 0);
-variable counter : std_logic_vector(63 downto 0);
+variable counter : unsigned(63 downto 0);
@@ -69,7 +68,7 @@ counter := (others => '0'); if begin_inst = '1' then
t(maxAddrBitIncIO downto 2):=sp;
t2:=pc;
- print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
+ print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));
end if;
wait until clk = '0';
|
