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author | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
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committer | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
commit | 0bf783475d6610a14f71884737aeae33246bb9be (patch) | |
tree | 8545a4d2e76761131f4945db6eeca7b563f7161e /zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj | |
parent | bf4405c61a9c010a8e888da678436a282b9551a3 (diff) | |
download | zpu-0bf783475d6610a14f71884737aeae33246bb9be.zip zpu-0bf783475d6610a14f71884737aeae33246bb9be.tar.gz |
add: ZPU reference designs for zealot
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj')
-rw-r--r-- | zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj new file mode 100644 index 0000000..81d56ef --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj @@ -0,0 +1,18 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl |