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author | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
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committer | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
commit | 0bf783475d6610a14f71884737aeae33246bb9be (patch) | |
tree | 8545a4d2e76761131f4945db6eeca7b563f7161e /zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh | |
parent | bf4405c61a9c010a8e888da678436a282b9551a3 (diff) | |
download | zpu-0bf783475d6610a14f71884737aeae33246bb9be.zip zpu-0bf783475d6610a14f71884737aeae33246bb9be.tar.gz |
add: ZPU reference designs for zealot
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh')
-rwxr-xr-x | zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh new file mode 100755 index 0000000..66622ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd +map -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. |