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| author | Bert Lange <b.lange@hzdr.de> | 2011-10-22 08:49:57 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-22 08:49:57 +0200 |
| commit | 73c11e7ba18d3415d61d03c4a1da588fe77e0466 (patch) | |
| tree | ccab850f55ade9690a4724ff888aa9687659d31c /zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut | |
| parent | 66a60bf34fd1960bb3c8f87a784dd2e6d27e2213 (diff) | |
| download | zpu-73c11e7ba18d3415d61d03c4a1da588fe77e0466.zip zpu-73c11e7ba18d3415d61d03c4a1da588fe77e0466.tar.gz | |
add: one more ZPU reference design for zealot
Diffstat (limited to 'zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut')
| -rw-r--r-- | zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut new file mode 100644 index 0000000..e0159fb --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut @@ -0,0 +1,39 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:2 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ConfigFallback:Enable +-g SelectMAPAbort:Enable +-g BPI_page_size:1 +-g OverTempPowerDown:Disable +-g JTAG_SysMon:Enable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No |
