diff options
| author | Bert Lange <b.lange@fzd.de> | 2011-11-07 15:41:50 +0100 |
|---|---|---|
| committer | Bert Lange <b.lange@fzd.de> | 2011-11-07 15:41:50 +0100 |
| commit | d190f1c37139ec38667a3d6e566dbe1b0549f84d (patch) | |
| tree | 7885f39318cb7852afc24992dd08cb6bb953ac03 /uc_str912/prj_test_lcd | |
| parent | acc2681723f43b3c8ccb29055bec9d63cb863c78 (diff) | |
| download | zpu-d190f1c37139ec38667a3d6e566dbe1b0549f84d.zip zpu-d190f1c37139ec38667a3d6e566dbe1b0549f84d.tar.gz | |
initial commit
Diffstat (limited to 'uc_str912/prj_test_lcd')
25 files changed, 6141 insertions, 0 deletions
diff --git a/uc_str912/prj_test_lcd/Makefile b/uc_str912/prj_test_lcd/Makefile new file mode 100644 index 0000000..9bfbf4e --- /dev/null +++ b/uc_str912/prj_test_lcd/Makefile @@ -0,0 +1,496 @@ +# Hey Emacs, this is a -*- makefile -*-
+#
+# WinARM template makefile
+# by Giacomo Fazio and Antonio Nasca, Catania, Italy
+# <giacomofazio@gmail.com>
+# <antodani.nasca@hotmail.it>
+#
+# based on the WinARM template makefile written by Martin Thomas
+# Released to the Public Domain
+# Please read the make user manual!
+#
+#
+# On command line:
+#
+# make all = Make software.
+#
+# make clean = Clean out built project files.
+#
+# make program = Download the hex file to the device
+#
+# (TODO: make filename.s = Just compile filename.c into the assembler code only)
+#
+# To rebuild project do "make clean" then "make all".
+# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe)
+#TCHAIN = arm-elf
+TCHAIN = arm-none-eabi
+
+USE_THUMB_MODE = YES
+#USE_THUMB_MODE = NO
+
+# MCU name and submodel
+MCU = arm966e-s
+SUBMDL = STR91x
+
+## Create ROM-Image
+RUN_MODE=ROM_RUN
+## Create RAM-Image
+#RUN_MODE=RAM_RUN
+
+## not supported in this example:
+## Exception-Vector placement only supported for "ROM_RUN"
+## (placement settings ignored when using "RAM_RUN")
+## - Exception vectors in ROM:
+#VECTOR_LOCATION=VECTORS_IN_ROM
+## - Exception vectors in RAM:
+#VECTOR_LOCATION=VECTORS_IN_RAM
+
+
+# Target file name (without extension).
+TARGET = lcd
+
+# List C source files here. (C dependencies are automatically generated.)
+# use file-extension c for "c-only"-files
+SRC = src/$(TARGET).c str91x_lib/91x_scu.c str91x_lib/91x_gpio.c src/lcd_lib_91x.c
+
+# List C source files here which must be compiled in ARM-Mode.
+# use file-extension c for "c-only"-files
+SRCARM = src/vectors.c
+# thumb is possible too for vectors.c - keep ARM, TODO: profile
+
+# List C++ source files here.
+# use file-extension cpp for C++-files (use extension .cpp)
+CPPSRC =
+
+# List C++ source files here which must be compiled in ARM-Mode.
+# use file-extension cpp for C++-files (use extension .cpp)
+#CPPSRCARM = $(TARGET).cpp
+CPPSRCARM =
+
+# List Assembler source files here.
+# Make them always end in a capital .S. Files ending in a lowercase .s
+# will not be considered source files but generated files (assembler
+# output from the compiler), and will be deleted upon "make clean"!
+# Even though the DOS/Win* filesystem matches both .s and .S the same,
+# it will preserve the spelling of the filenames, and gcc itself does
+# care about how the name is spelled on its command-line.
+ASRC =
+
+# List Assembler source files here which must be assembled in ARM-Mode..
+ASRCARM = src/vector.S src/startup.S
+
+# Path to Linker-Scripts
+LINKERSCRIPTPATH = .
+
+## Output format. (can be ihex or binary or both)
+## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision)
+#FORMAT = ihex
+#FORMAT = binary
+FORMAT = both
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+#OPT = s
+OPT = 0
+
+## Using the Atmel AT91_lib produces warning with
+## the default warning-levels.
+## yes - disable these warnings; no - keep default settings
+#AT91LIBNOWARN = yes
+AT91LIBNOWARN = no
+
+# Debugging format.
+# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2.
+# AVR (extended) COFF requires stabs, plus an avr-objcopy run.
+#DEBUG = stabs
+DEBUG = dwarf-2
+
+# List any extra directories to look for include files here.
+# Each directory must be seperated by a space.
+EXTRAINCDIRS = ./include ./str91x_lib/include
+
+# List any extra directories to look for library files here.
+# Each directory must be seperated by a space.
+#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4
+EXTRA_LIBDIRS = ./str91x_lib
+
+
+# Compiler flag to set the C Standard level.
+# c89 - "ANSI" C
+# gnu89 - c89 plus GCC extensions
+# c99 - ISO C99 standard (not yet fully implemented)
+# gnu99 - c99 plus GCC extensions
+CSTANDARD = -std=gnu99
+
+# Place -D or -U options for C here
+CDEFS = -D$(RUN_MODE)
+
+# Place -I options here
+CINCS =
+
+# Place -D or -U options for ASM here
+ADEFS = -D$(RUN_MODE)
+
+ifdef VECTOR_LOCATION
+CDEFS += -D$(VECTOR_LOCATION)
+ADEFS += -D$(VECTOR_LOCATION)
+endif
+
+CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__
+
+# Compiler flags.
+
+ifeq ($(USE_THUMB_MODE),YES)
+THUMB = -mthumb
+THUMB_IW = -mthumb-interwork
+else
+THUMB =
+THUMB_IW =
+endif
+
+# -g*: generate debugging information
+# -O*: optimization level
+# -f...: tuning, see GCC manual and avr-libc documentation
+# -Wall...: warning level
+# -Wa,...: tell GCC to pass this to the assembler.
+# -adhlns...: create assembler listing
+#
+# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
+CFLAGS = -g$(DEBUG)
+CFLAGS += $(CDEFS) $(CINCS)
+CFLAGS += -O$(OPT)
+CFLAGS += -Wall -Wcast-align -Wimplicit
+CFLAGS += -Wpointer-arith -Wswitch
+CFLAGS += -ffunction-sections -fdata-sections
+CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused
+CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<)
+CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+
+# flags only for C
+CONLYFLAGS += -Wnested-externs
+CONLYFLAGS += $(CSTANDARD)
+
+ifneq ($(AT91LIBNOWARN),yes)
+#AT91-lib warnings with:
+CFLAGS += -Wcast-qual
+CONLYFLAGS += -Wmissing-prototypes
+CONLYFLAGS += -Wstrict-prototypes
+CONLYFLAGS += -Wmissing-declarations
+endif
+
+# flags only for C++ (arm-elf-g++)
+# CPPFLAGS = -fno-rtti -fno-exceptions
+CPPFLAGS =
+
+# Assembler flags.
+# -Wa,...: tell GCC to pass this to the assembler.
+# -ahlns: create listing
+# -g$(DEBUG): have the assembler create line number information
+ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG)
+
+
+#Additional libraries.
+
+# Extra libraries
+# Each library-name must be seperated by a space.
+# To add libxyz.a, libabc.a and libefsl.a:
+# EXTRA_LIBS = xyz abc efsl
+#EXTRA_LIBS = efsl
+EXTRA_LIBS =
+#STR91x_lib
+
+#Support for newlibc-lpc (file: libnewlibc-lpc.a)
+#NEWLIBLPC = -lnewlib-lpc
+
+MATH_LIB = -lm
+
+# CPLUSPLUS_LIB = -lstdc++
+
+
+# Linker flags.
+# -Wl,...: tell GCC to pass this to linker.
+# -Map: create map file
+# --cref: add cross reference to map file
+LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections,--no-warn-mismatch
+LDFLAGS += -lc
+LDFLAGS += $(NEWLIBLPC) $(MATH_LIB)
+LDFLAGS += -lc -lgcc
+LDFLAGS += $(CPLUSPLUS_LIB)
+LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS))
+LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS))
+
+# Set Linker-Script Depending On Selected Memory and Controller
+ifeq ($(RUN_MODE),RAM_RUN)
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld
+else
+LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld
+endif
+
+
+# Define directories, if needed.
+## DIRARM = c:/WinARM/
+## DIRARMBIN = $(DIRAVR)/bin/
+## DIRAVRUTILS = $(DIRAVR)/utils/bin/
+
+# Define programs and commands.
+SHELL = sh
+CC = $(TCHAIN)-gcc
+CPP = $(TCHAIN)-g++
+AR = $(TCHAIN)-ar
+OBJCOPY = $(TCHAIN)-objcopy
+OBJDUMP = $(TCHAIN)-objdump
+SIZE = $(TCHAIN)-size
+NM = $(TCHAIN)-nm
+REMOVE = rm -f
+REMOVEDIR = rm -f -r
+COPY = cp
+
+# Define Messages
+# English
+MSG_ERRORS_NONE = Errors: none
+MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------"
+MSG_END = -------- end --------
+MSG_SIZE_BEFORE = Size before:
+MSG_SIZE_AFTER = Size after:
+MSG_FLASH = Creating load file for Flash:
+MSG_EXTENDED_LISTING = Creating Extended Listing:
+MSG_SYMBOL_TABLE = Creating Symbol Table:
+MSG_LINKING = Linking:
+MSG_COMPILING = Compiling C:
+MSG_COMPILING_ARM = "Compiling C (ARM-only):"
+MSG_COMPILINGCPP = Compiling C++:
+MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):"
+MSG_ASSEMBLING = Assembling:
+MSG_ASSEMBLING_ARM = "Assembling (ARM-only):"
+MSG_CLEANING = Cleaning project:
+MSG_FORMATERROR = Can not handle output-format
+MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now.
+
+# Define all object files.
+COBJ = $(SRC:.c=.o)
+AOBJ = $(ASRC:.S=.o)
+COBJARM = $(SRCARM:.c=.o)
+AOBJARM = $(ASRCARM:.S=.o)
+CPPOBJ = $(CPPSRC:.cpp=.o)
+CPPOBJARM = $(CPPSRCARM:.cpp=.o)
+
+# Define all listing files.
+LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst)
+LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst)
+
+# Compiler flags to generate dependency files.
+### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d
+GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d
+
+# Combine all necessary flags and optional flags.
+# Add target processor to flags.
+ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS)
+ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS)
+
+
+# Default target.
+all: begin gccversion sizebefore build sizeafter finished end
+
+ifeq ($(FORMAT),ihex)
+build: elf hex lss sym
+hex: $(TARGET).hex
+IMGEXT=hex
+else
+ifeq ($(FORMAT),binary)
+build: elf bin lss sym
+bin: $(TARGET).bin
+IMGEXT=bin
+else
+ifeq ($(FORMAT),both)
+build: elf hex bin lss sym
+hex: $(TARGET).hex
+bin: $(TARGET).bin
+else
+$(error "$(MSG_FORMATERROR) $(FORMAT)")
+endif
+endif
+endif
+
+elf: $(TARGET).elf
+lss: $(TARGET).lss
+sym: $(TARGET).sym
+
+# Eye candy.
+begin:
+ @echo
+ @echo $(MSG_BEGIN)
+
+finished:
+ @echo $(MSG_ERRORS_NONE)
+
+end:
+ @echo $(MSG_END)
+ @echo
+
+
+# Display size of file.
+HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
+ELFSIZE = $(SIZE) -A $(TARGET).elf
+sizebefore:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi
+
+sizeafter:
+ @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi
+
+
+# Display compiler version information.
+gccversion :
+ @$(CC) --version
+
+# FLASH Programming with OPENOCD
+
+# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe)
+# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded
+OPENOCD_DIR = 'c:\Programmi\openocd\bin\'
+
+# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger)
+OPENOCD = $(OPENOCD_DIR)openocd-pp.exe
+#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe
+
+# specify OpenOCD configuration file (pick the one for your device)
+#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_signalyzer-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_jtagkey-flash-program.cfg
+#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_armusbocd-flash-program.cfg
+OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_pp-flash-program.cfg
+
+program:
+ @echo
+ @echo "Flash Programming with OpenOCD..."
+ $(OPENOCD) -f $(OPENOCD_CFG)
+ @echo
+ @echo
+ @echo "Flash Programming Finished."
+
+
+# Create final output file (.hex) from ELF output file.
+%.hex: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O ihex $< $@
+
+# Create final output file (.bin) from ELF output file.
+%.bin: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O binary $< $@
+
+
+# Create extended listing file from ELF output file.
+# testing: option -C
+%.lss: %.elf
+ @echo
+ @echo $(MSG_EXTENDED_LISTING) $@
+ $(OBJDUMP) -h -S -C $< > $@
+
+
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+ @echo
+ @echo $(MSG_SYMBOL_TABLE) $@
+ $(NM) -n $< > $@
+
+
+# Link: create ELF output file from object files.
+.SECONDARY : $(TARGET).elf
+.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
+ @echo
+ @echo $(MSG_LINKING) $@
+ $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
+
+# Compile: create object files from C source files. ARM/Thumb
+$(COBJ) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING) $<
+ $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C source files. ARM-only
+$(COBJARM) : %.o : %.c
+ @echo
+ @echo $(MSG_COMPILING_ARM) $<
+ $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM/Thumb
+$(CPPOBJ) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP) $<
+ $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+# Compile: create object files from C++ source files. ARM-only
+$(CPPOBJARM) : %.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILINGCPP_ARM) $<
+ $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C source files. ARM/Thumb
+## does not work - TODO - hints welcome
+##$(COBJ) : %.s : %.c
+## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM/Thumb
+$(AOBJ) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING) $<
+ $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files. ARM-only
+$(AOBJARM) : %.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING_ARM) $<
+ $(CC) -c $(ALL_ASFLAGS) $< -o $@
+
+
+# Target: clean project.
+clean: begin clean_list finished end
+
+
+clean_list :
+ @echo
+ @echo $(MSG_CLEANING)
+ $(REMOVE) $(TARGET).hex
+ $(REMOVE) $(TARGET).bin
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).elf
+ $(REMOVE) $(TARGET).map
+ $(REMOVE) $(TARGET).obj
+ $(REMOVE) $(TARGET).a90
+ $(REMOVE) $(TARGET).sym
+ $(REMOVE) $(TARGET).lnk
+ $(REMOVE) $(TARGET).lss
+ $(REMOVE) $(COBJ)
+ $(REMOVE) $(CPPOBJ)
+ $(REMOVE) $(AOBJ)
+ $(REMOVE) $(COBJARM)
+ $(REMOVE) $(CPPOBJARM)
+ $(REMOVE) $(AOBJARM)
+ $(REMOVE) $(LST)
+ $(REMOVE) $(SRC:.c=.s)
+ $(REMOVE) $(SRC:.c=.d)
+ $(REMOVE) $(SRCARM:.c=.s)
+ $(REMOVE) $(SRCARM:.c=.d)
+ $(REMOVE) $(CPPSRC:.cpp=.s)
+ $(REMOVE) $(CPPSRC:.cpp=.d)
+ $(REMOVE) $(CPPSRCARM:.cpp=.s)
+ $(REMOVE) $(CPPSRCARM:.cpp=.d)
+ $(REMOVEDIR) .dep | exit 0
+
+
+# Include the dependency files.
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+
+# Listing of phony targets.
+.PHONY : all begin finish end sizebefore sizeafter gccversion \
+build elf hex bin lss sym clean clean_list program
+
diff --git a/uc_str912/prj_test_lcd/STR91x-ROM.ld b/uc_str912/prj_test_lcd/STR91x-ROM.ld new file mode 100644 index 0000000..ed2979b --- /dev/null +++ b/uc_str912/prj_test_lcd/STR91x-ROM.ld @@ -0,0 +1,221 @@ +/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/* Stack Sizes */
+
+ _STACKSIZE = 1024;
+ _STACKSIZE_IRQ = 256;
+ _STACKSIZE_FIQ = 256;
+ _STACKSIZE_SVC = 0;
+ _STACKSIZE_ABT = 0;
+ _STACKSIZE_UND = 0;
+ _HEAPSIZE = 1024;
+
+/* Memory Definitions */
+
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
+ DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000
+}
+
+/* Section Definitions */
+
+SECTIONS
+{
+ /* first section is .text which is used for code */
+
+ .text :
+ {
+ KEEP(*(.vectors))
+ KEEP(*(.init))
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t .glue_7)
+ KEEP(*(.fini))
+ *(.gcc_except_table)
+ } >CODE =0
+ . = ALIGN(4);
+
+ /* .ctors .dtors are used for c++ constructors/destructors */
+
+ .ctors :
+ {
+ PROVIDE(__ctors_start__ = .);
+ KEEP(*(SORT(.ctors.*)))
+ KEEP(*(.ctors))
+ PROVIDE(__ctors_end__ = .);
+ } >CODE
+
+ .dtors :
+ {
+ PROVIDE(__dtors_start__ = .);
+ KEEP(*(SORT(.dtors.*)))
+ KEEP(*(.dtors))
+ PROVIDE(__dtors_end__ = .);
+ } >CODE
+
+ /* .rodata section which is used for read-only data (constants) */
+
+ .rodata :
+ {
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >CODE
+ . = ALIGN(4);
+
+ _etext = .;
+ PROVIDE (etext = .);
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_etext)
+ {
+ __data_start = .;
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ . = ALIGN(4);
+ *(.fastrun .fastrun.*)
+ } >DATA
+ . = ALIGN(4);
+
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* .bss section which is used for uninitialized data */
+
+ .bss :
+ {
+ __bss_start = .;
+ __bss_start__ = .;
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >DATA
+ . = ALIGN(4);
+ __bss_end__ = .;
+
+ _end = .;
+ PROVIDE(end = .);
+
+ /* .heap section which is used for memory allocation */
+
+ .heap (NOLOAD) :
+ {
+ __heap_start__ = .;
+ *(.heap)
+ . = MAX(__heap_start__ + _HEAPSIZE , .);
+ } >DATA
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ /* .stack section - user mode stack */
+
+ .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_start__ = .;
+ *(.stack)
+ . = MAX(__stack_start__ + _STACKSIZE , .);
+ } >DATA
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ /* .stack_irq section */
+
+ .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq)
+ . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .);
+ } >DATA
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ /* .stack_fiq section */
+
+ .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq)
+ . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .);
+ } >DATA
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ /* .stack_svc section */
+
+ .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc)
+ . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .);
+ } >DATA
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ /* .stack_abt section */
+
+ .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt)
+ . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .);
+ } >DATA
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ /* .stack_und section */
+
+ .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) :
+ {
+ __stack_und_start__ = .;
+ *(.stack_und)
+ . = MAX(__stack_und_start__ + _STACKSIZE_UND , .);
+ } >DATA
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
diff --git a/uc_str912/prj_test_lcd/include/91x_ahbapb.h b/uc_str912/prj_test_lcd/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_ahbapb.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file contains all the functions prototypes for the
+* AHBAPB software library.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _91x_AHBAPB_H
+#define _91x_AHBAPB_H
+
+#include "91x_map.h"
+
+#define AHBAPB_Split_Enable 0x01000000
+#define AHBAPB_Split_Disable 0xFEFFFFFF
+#define AHBAPB_Error_Enable 0x0000100
+#define AHBAPB_Error_Disable 0xFFFFEFF
+
+/*FLAG*/
+#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/
+#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */
+#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */
+#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/
+
+/* Includes ------------------------------------------------------------------*/
+
+
+/* AHBAPB Init structure definition */
+typedef struct
+{
+ u32 AHBAPB_SetTimeOut;
+ u32 AHBAPB_Error;
+ u32 AHBAPB_Split;
+ u8 AHBAPB_SplitCounter;
+}AHBAPB_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx);
+void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct);
+void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct);
+FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
+void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
+u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx);
+
+
+#endif /* _91x_AHBAPB_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/91x_conf.h b/uc_str912/prj_test_lcd/include/91x_conf.h new file mode 100644 index 0000000..578335d --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_conf.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_conf.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : Library configuration.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+
+#ifndef __91x_CONF_H
+#define __91x_CONF_H
+
+/* To work in buffered mode just decomment the following line */
+
+//#define Buffered
+
+/* Comment the line below to put the library in release mode */
+//#define DEBUG
+
+/************************* AHBAPB *************************/
+//#define _AHBAPB
+//#define _AHBAPB0
+//#define _AHBAPB1
+/************************* VIC *************************/
+//#define _VIC
+//#define _VIC0
+//#define _VIC1
+/************************* DMA *************************/
+//#define _DMA
+//#define _DMA_Channel0
+//#define _DMA_Channel1
+//#define _DMA_Channel2
+//#define _DMA_Channel3
+//#define _DMA_Channel4
+//#define _DMA_Channel5
+//#define _DMA_Channel6
+//#define _DMA_Channel7
+
+/************************* EMI *************************/
+//#define _EMI
+//#define _EMI_Bank0
+//#define _EMI_Bank1
+//#define _EMI_Bank2
+//#define _EMI_Bank3
+/************************* FMI *************************/
+//#define _FMI
+/************************* WIU *************************/
+//#define _WIU
+/************************* TIM *************************/
+//#define _TIM
+//#define _TIM0
+//#define _TIM1
+//#define _TIM2
+//#define _TIM3
+/************************* GPIO ************************/
+#define _GPIO
+#define _GPIO0
+#define _GPIO1
+#define _GPIO2
+#define _GPIO3
+#define _GPIO4
+#define _GPIO5
+#define _GPIO6
+#define _GPIO7
+#define _GPIO8
+#define _GPIO9
+/************************* RTC *************************/
+//#define _RTC
+/************************* SCU *************************/
+#define _SCU
+/************************* MC **************************/
+//#define _MC
+/************************* UART ************************/
+//#define _UART
+//#define _UART0
+//#define _UART1
+//#define _UART2
+/************************* SSP *************************/
+//#define _SSP
+//#define _SSP0
+//#define _SSP1
+/************************* CAN *************************/
+//#define _CAN
+/************************* ADC *************************/
+//#define _ADC
+/************************* WDG *************************/
+//#define _WDG
+/************************* I2C *************************/
+//#define _I2C
+//#define _I2C0
+//#define _I2C1
+/************************ ENET *************************/
+//#define _ENET
+
+/*---------------------------- _Main_Crystal frequency value (KHz)------------*/
+
+#ifndef _Main_Crystal
+#define _Main_Crystal 25000
+#endif
+/*------------------------------------------------------------------------------*/
+
+
+#endif /* __91x_CONF_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/91x_fmi.h b/uc_str912/prj_test_lcd/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_fmi.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file contains all the functions prototypes for the
+* FMI software library.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+
+/* Define to prevent recursive inclusion ------------------------------------ */
+
+#ifndef __91x_FMI_H
+#define __91x_FMI_H
+
+/* ========================================================================== */
+/* When bank 1 is remapped at address 0x0, decomment the following line */
+/* ========================================================================== */
+
+//#define Remap_Bank_1
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "91x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* FMI banks */
+
+#ifdef Remap_Bank_1
+
+#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */
+#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */
+
+#else /* Remap Bank 0 */
+
+#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */
+#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */
+
+#endif
+
+/* FMI sectors */
+
+#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */
+#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */
+#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */
+#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */
+#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */
+#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */
+#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */
+#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */
+
+#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
+#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */
+#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */
+#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */
+
+/* FMI Flags */
+
+#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */
+#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */
+#define FMI_FLAG_PS 0x10 /* Program Status Flag */
+#define FMI_FLAG_ES 0x20 /* Erase Status Flag */
+#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */
+#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */
+
+/* FMI read wait states */
+
+#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */
+#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */
+#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */
+
+/* FMI write wait states */
+
+#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */
+#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */
+
+/* FMI power down configuration */
+
+#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */
+#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */
+
+/* FMI low voltage detector */
+
+#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */
+#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */
+
+/* FMI frequency range */
+
+#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */
+#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */
+ /* Above 66 MHz*/
+/* FMI OTP word addresses */
+
+#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */
+#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */
+#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */
+#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */
+#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */
+#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */
+#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */
+#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */
+
+/* FMI OTP halfword addresses */
+
+#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */
+#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */
+#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */
+#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */
+#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */
+#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */
+#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */
+#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */
+#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */
+#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */
+#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */
+#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */
+#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */
+#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */
+#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */
+#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */
+
+/* FMI sectors Masks */
+
+#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */
+#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */
+#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */
+#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */
+#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */
+#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */
+#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */
+#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */
+
+#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */
+#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */
+#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */
+#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */
+
+/* Timeout error */
+
+#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */
+#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */
+
+/* Module private variables --------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
+ u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress);
+void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
+ u16 FMI_LVDEN, u16 FMI_FreqRange);
+void FMI_EraseSector(vu32 FMI_Sector);
+void FMI_EraseBank(vu32 FMI_Bank);
+void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data);
+void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData);
+u32 FMI_ReadWord(u32 FMI_Address);
+u32 FMI_ReadOTPData(u8 FMI_OTPAddress);
+FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank);
+u16 FMI_GetReadWaitStateValue(void);
+u16 FMI_GetWriteWaitStateValue(void);
+void FMI_SuspendEnable(vu32 FMI_Bank);
+void FMI_ResumeEnable(vu32 FMI_Bank);
+void FMI_ClearFlag(vu32 FMI_Bank);
+void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState);
+FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection);
+u8 FMI_WaitForLastOperation(vu32 FMI_Bank);
+
+#endif /* __91x_FMI_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
+
diff --git a/uc_str912/prj_test_lcd/include/91x_gpio.h b/uc_str912/prj_test_lcd/include/91x_gpio.h new file mode 100644 index 0000000..4beab75 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_gpio.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file contains all the functions prototypes for the
+* GPIO software library.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion ------------------------------------ */
+
+#ifndef _91x_GPIO_H
+#define _91x_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_map.h"
+
+/* GPIO Init structure definition */
+typedef struct
+{
+ u8 GPIO_Pin;
+ u8 GPIO_Direction;
+ u8 GPIO_Type;
+ u8 GPIO_IPConnected;
+ u16 GPIO_Alternate;
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+
+/* Exported constants --------------------------------------------------------*/
+#define GPIO_Pin_None 0x00
+#define GPIO_Pin_0 0x01
+#define GPIO_Pin_1 0x02
+#define GPIO_Pin_2 0x04
+#define GPIO_Pin_3 0x08
+#define GPIO_Pin_4 0x10
+#define GPIO_Pin_5 0x20
+#define GPIO_Pin_6 0x40
+#define GPIO_Pin_7 0x80
+#define GPIO_Pin_All 0xFF
+
+#define GPIO_PinInput 0x00
+#define GPIO_PinOutput 0x01
+
+#define GPIO_Type_PushPull 0x00
+#define GPIO_Type_OpenCollector 0x01
+
+#define GPIO_IPConnected_Disable 0x00
+#define GPIO_IPConnected_Enable 0x01
+
+#define GPIO_InputAlt1 0x00
+#define GPIO_OutputAlt1 0x01
+#define GPIO_OutputAlt2 0x02
+#define GPIO_OutputAlt3 0x03
+
+#define GPIO_ANAChannel0 0x01
+#define GPIO_ANAChannel1 0x02
+#define GPIO_ANAChannel2 0x04
+#define GPIO_ANAChannel3 0x08
+#define GPIO_ANAChannel4 0x10
+#define GPIO_ANAChannel5 0x20
+#define GPIO_ANAChannel6 0x40
+#define GPIO_ANAChannel7 0x80
+#define GPIO_ANAChannelALL 0xFF
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin);
+u8 GPIO_Read(GPIO_TypeDef* GPIOx);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal);
+void GPIO_EMIConfig(FunctionalState NewState);
+void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState);
+
+#endif /* _91x_GPIO_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/91x_lib.h b/uc_str912/prj_test_lcd/include/91x_lib.h new file mode 100644 index 0000000..823b250 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_lib.h @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_lib.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : Used to include the peripherals header file in the
+* user application.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+#ifndef __91x_LIB_H
+#define __91x_LIB_H
+
+#include "91x_map.h"
+#include "91x_conf.h"
+
+#ifdef _AHBAPB
+ #include "91x_ahbapb.h"
+#endif /* _AHBAPB */
+
+#ifdef _EMI
+ #include "91x_emi.h"
+#endif /* _EMI */
+
+#ifdef _DMA
+ #include "91x_dma.h"
+#endif /* _DMA */
+
+#ifdef _FMI
+ #include "91x_fmi.h"
+#endif /* _FMI */
+
+#ifdef _VIC
+ #include "91x_vic.h"
+#endif /* _VIC */
+
+#ifdef _WIU
+ #include "91x_wiu.h"
+#endif /* _WIU */
+
+#ifdef _TIM
+ #include "91x_tim.h"
+#endif /* _TIM */
+
+#ifdef _GPIO
+ #include "91x_gpio.h"
+#endif /* _GPIO */
+
+#ifdef _RTC
+ #include "91x_rtc.h"
+#endif /* _RTC */
+
+#ifdef _SCU
+ #include "91x_scu.h"
+#endif /* _SCU */
+
+#ifdef _UART
+ #include "91x_uart.h"
+#endif /* _UART */
+
+#ifdef _SSP
+ #include "91x_ssp.h"
+#endif /* _SSP */
+
+#ifdef _CAN
+ #include "91x_can.h"
+#endif /* _CAN */
+
+#ifdef _ADC
+ #include "91x_adc.h"
+#endif /* _ADC */
+
+#ifdef _WDG
+ #include "91x_wdg.h"
+#endif /* _WDG */
+
+#ifdef _I2C
+ #include "91x_i2c.h"
+#endif /* _I2C */
+
+#ifdef _WIU
+ #include "91x_wiu.h"
+#endif
+
+#ifdef _MC
+ #include "91x_mc.h"
+#endif
+
+#ifdef _ENET
+ #include "91x_enet.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Module private variables --------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+ void debug( void );
+
+
+#endif /* __91x_LIB_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/91x_map.h b/uc_str912/prj_test_lcd/include/91x_map.h new file mode 100644 index 0000000..2e94a91 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_map.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : Peripherals registers definition and memory mapping.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion ------------------------------------ */
+#ifndef __91x_MAP_H
+#define __91x_MAP_H
+
+#ifndef EXT
+ #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_conf.h"
+#include "91x_type.h"
+
+/******************************************************************************/
+/* IP registers structures */
+/******************************************************************************/
+
+/*------------------------------------ FMI -----------------------------------*/
+
+typedef struct
+{
+ vu32 BBSR; /* Boot Bank Size Register */
+ vu32 NBBSR; /* Non-Boot Bank Size Register */
+ vu32 EMPTY1;
+ vu32 BBADR; /* Boot Bank Base Address Register */
+ vu32 NBBADR; /* Non-Boot Bank Base Address Register */
+ vu32 EMPTY2;
+ vu32 CR; /* Control Register */
+ vu32 SR; /* Status Register */
+ vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
+} FMI_TypeDef;
+
+/*---------------------- Analog to Digital Convertor ------------------------*/
+
+typedef struct
+{
+ vu16 CR; /* Control Register */
+ vu16 EMPTY1;
+ vu16 CCR; /* Channel Configuration Register */
+ vu16 EMPTY2;
+ vu16 HTR; /* Higher Threshold Register */
+ vu16 EMPTY3;
+ vu16 LTR; /* Lower Threshold Register */
+ vu16 EMPTY4;
+ vu16 CRR; /* Compare Result Register */
+ vu16 EMPTY5;
+ vu16 DR0; /* Data Register for Channel 0 */
+ vu16 EMPTY6;
+ vu16 DR1; /* Data Register for Channel 1 */
+ vu16 EMPTY7;
+ vu16 DR2; /* Data Register for Channel 2 */
+ vu16 EMPTY8;
+ vu16 DR3; /* Data Register for Channel 3 */
+ vu16 EMPTY9;
+ vu16 DR4; /* Data Register for Channel 4 */
+ vu16 EMPTY10;
+ vu16 DR5; /* Data Register for Channel 5 */
+ vu16 EMPTY11;
+ vu16 DR6; /* Data Register for Channel 6 */
+ vu16 EMPTY12;
+ vu16 DR7; /* Data Register for Channel 7 */
+ vu16 EMPTY13;
+ vu16 PRS; /* Prescaler Value Register */
+ vu16 EMPTY14;
+} ADC_TypeDef;
+
+/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
+
+typedef struct
+{
+ vu32 BSR; /* Bridge Status Register */
+ vu32 BCR; /* Bridge Configuration Register */
+ vu32 PAER; /* Peripheral Address Error register */
+} AHBAPB_TypeDef;
+
+/*--------------- Controller Area Network Interface Register -----------------*/
+
+typedef struct
+{
+ vu16 CRR; /* IFn Command request Register */
+ vu16 EMPTY1;
+ vu16 CMR; /* IFn Command Mask Register */
+ vu16 EMPTY2;
+ vu16 M1R; /* IFn Message Mask 1 Register */
+ vu16 EMPTY3;
+ vu16 M2R; /* IFn Message Mask 2 Register */
+ vu16 EMPTY4;
+ vu16 A1R; /* IFn Message Arbitration 1 Register */
+ vu16 EMPTY5;
+ vu16 A2R; /* IFn Message Arbitration 2 Register */
+ vu16 EMPTY6;
+ vu16 MCR; /* IFn Message Control Register */
+ vu16 EMPTY7;
+ vu16 DA1R; /* IFn DATA A 1 Register */
+ vu16 EMPTY8;
+ vu16 DA2R; /* IFn DATA A 2 Register */
+ vu16 EMPTY9;
+ vu16 DB1R; /* IFn DATA B 1 Register */
+ vu16 EMPTY10;
+ vu16 DB2R; /* IFn DATA B 2 Register */
+ vu16 EMPTY11[27];
+} CAN_MsgObj_TypeDef;
+
+typedef struct
+{
+ vu16 CR; /* Control Register */
+ vu16 EMPTY1;
+ vu16 SR; /* Status Register */
+ vu16 EMPTY2;
+ vu16 ERR; /* Error counter Register */
+ vu16 EMPTY3;
+ vu16 BTR; /* Bit Timing Register */
+ vu16 EMPTY4;
+ vu16 IDR; /* Interrupt Identifier Register */
+ vu16 EMPTY5;
+ vu16 TESTR; /* Test Register */
+ vu16 EMPTY6;
+ vu16 BRPR; /* BRP Extension Register */
+ vu16 EMPTY7[3];
+ CAN_MsgObj_TypeDef sMsgObj[2];
+ vu16 EMPTY8[16];
+ vu16 TXR1R; /* Transmission request 1 Register */
+ vu16 EMPTY9;
+ vu16 TXR2R; /* Transmission Request 2 Register */
+ vu16 EMPTY10[13];
+ vu16 ND1R; /* New Data 1 Register */
+ vu16 EMPTY11;
+ vu16 ND2R; /* New Data 2 Register */
+ vu16 EMPTY12[13];
+ vu16 IP1R; /* Interrupt Pending 1 Register */
+ vu16 EMPTY13;
+ vu16 IP2R; /* Interrupt Pending 2 Register */
+ vu16 EMPTY14[13];
+ vu16 MV1R; /* Message Valid 1 Register */
+ vu16 EMPTY15;
+ vu16 MV2R; /* Message VAlid 2 Register */
+ vu16 EMPTY16;
+} CAN_TypeDef;
+
+/*----------------------- System Control Unit---------------------------------*/
+
+typedef struct
+{
+ vu32 CLKCNTR; /* Clock Control Register */
+ vu32 PLLCONF; /* PLL Configuration Register */
+ vu32 SYSSTATUS; /* System Status Register */
+ vu32 PWRMNG; /* Power Management Register */
+ vu32 ITCMSK; /* Interrupt Mask Register */
+ vu32 PCGRO; /* Peripheral Clock Gating Register 0 */
+ vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
+ vu32 PRR0; /* Peripheral Reset Register 0 */
+ vu32 PRR1; /* Peripheral Reset Register 1 */
+ vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
+ vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
+ vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
+ vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
+ vu32 SCR0; /* System Configuration Register 0 */
+ vu32 SCR1; /* System Configuration Register 1 */
+ vu32 SCR2; /* System Configuration Register 2 */
+ u32 EMPTY1;
+ vu32 GPIOOUT[8]; /* GPIO Output Registers */
+ vu32 GPIOIN[8]; /* GPIO Input Registers */
+ vu32 GPIOTYPE[10];/* GPIO Type Registers */
+ vu32 GPIOEMI; /* GPIO EMI Selector Register */
+ vu32 WKUPSEL; /* Wake-Up Selection Register */
+ u32 EMPTY2[2];
+ vu32 GPIOANA; /* GPIO Analag mode Register */
+} SCU_TypeDef;
+
+/*------------------------- DMA Channelx Registers ---------------------------*/
+
+typedef struct
+{
+ vu32 SRC; /* Channelx Source Address Register */
+ vu32 DES; /* Channelx Destination Address Register */
+ vu32 LLI; /* Channelx Lincked List Item Register */
+ vu32 CC; /* Channelx Contol Register */
+ vu32 CCNF; /* Channelx Configuration Register */
+} DMA_Channel_TypeDef;
+
+/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
+
+/*----------------------------- DMA Controller -------------------------------*/
+
+typedef struct
+{
+ vu32 ISR; /* Interrupt Status Register */
+ vu32 TCISR; /* Terminal Count Interrupt Status Register */
+ vu32 TCICR; /* Terminal CountInterrupt Clear Register */
+ vu32 EISR; /* Error Interrupt Status Register */
+ vu32 EICR; /* Error Interrupt Clear Register */
+ vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
+ vu32 ERISR; /* Raw Error Interrupt Status Register */
+ vu32 ENCSR; /* Enabled Channel Status Register */
+ vu32 SBRR; /* Software Burst Request Register */
+ vu32 SSRR; /* Software Single Request Register */
+ vu32 SLBRR; /* Software Last Burst Request Register */
+ vu32 SLSRR; /* Software Last Single Request Register */
+ vu32 CNFR; /* Configuration Register */
+ vu32 SYNR; /* Syncronization Register */
+ } DMA_TypeDef;
+
+/*--------------------------------- TIM Timer --------------------------------*/
+
+typedef struct
+{
+ vu16 IC1R; /* Input Capture 1 Register */
+ vu16 EMPTY1;
+ vu16 IC2R; /* Input Capture 2 Register */
+ vu16 EMPTY2;
+ vu16 OC1R; /* Output Compare 1 Register */
+ vu16 EMPTY3;
+ vu16 OC2R; /* Output Compare 2 Register */
+ vu16 EMPTY4;
+ vu16 CNTR; /* Counter Register */
+ vu16 EMPTY5;
+ vu16 CR1; /* Control Register 1 */
+ vu16 EMPTY6;
+ vu16 CR2; /* Control Register 2 */
+ vu16 EMPTY7;
+ vu16 SR; /* Status Register */
+ vu16 EMPTY8;
+} TIM_TypeDef;
+
+/*---------------------------- EMI Bankx Registers ---------------------------*/
+
+typedef struct
+{
+ vu32 ICR; /* Bankx Idle Cycle Control Register */
+ vu32 RCR; /* Bankx Read Wait State Control Register */
+ vu32 WCR; /* Bankx Write Wait State Control Register */
+ vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
+ vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
+ vu32 BCR; /* Bankx Control Register */
+ } EMI_Bank_TypeDef;
+
+/*---------------------------- Ethernet Controller ---------------------------*/
+
+/* MAC Registers */
+typedef struct
+{
+ vu32 MCR; /* ENET Control Register */
+ vu32 MAH; /* ENET Address High Register */
+ vu32 MAL; /* ENET Address Low Register */
+ vu32 MCHA; /* Multicast Address High Register */
+ vu32 MCLA; /* Multicast Address Low Register */
+ vu32 MIIA; /* MII Address Register */
+ vu32 MIID; /* MII Data Register */
+ vu32 MCF; /* ENET Control Frame Register */
+ vu32 VL1; /* VLAN1 Register */
+ vu32 VL2; /* VLAN2 register */
+ vu32 MTS; /* ENET Transmission Status Register */
+ vu32 MRS; /* ENET Reception Status Register */
+} ENET_MAC_TypeDef;
+
+/* DMA Registers */
+typedef struct
+{
+ vu32 SCR; /* DMA Status and Control Register */
+ vu32 IER; /* DMA Interrupt Sources Enable Register */
+ vu32 ISR; /* DMA Interrupt Status Register */
+ vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
+ ENET_CLK phase relations */
+ vu32 RXSTR; /* Rx DMA start Register */
+ vu32 RXCR; /* Rx DMA Control Register */
+ vu32 RXSAR; /* Rx DMA Base Address Register */
+ vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
+ vu32 RXCAR; /* Rx DMA Current Address Register */
+ vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
+ vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
+ vu32 RXSR; /* Rx DMA FIFO Status Register */
+ vu32 TXSTR; /* Tx DMA start Register */
+ vu32 TXCR; /* Tx DMA Control Register */
+ vu32 TXSAR; /* Tx DMA Base Address Register */
+ vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
+ vu32 TXCAR; /* Tx DMA Current Address Register */
+ vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
+ vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
+ vu32 TXSR; /* Tx DMA FIFO Status Register */
+} ENET_DMA_TypeDef;
+
+/*------------------------------------- GPIO ---------------------------------*/
+
+typedef struct
+{
+ vu8 DR[1021]; /* Data Register */
+ vu32 DDR; /* Data Direction Register */
+} GPIO_TypeDef;
+
+/*-------------------------------- I2C interface -----------------------------*/
+
+typedef struct
+{
+ vu8 CR; /* Control Register */
+ vu8 EMPTY1[3];
+ vu8 SR1; /* Status Register 1 */
+ vu8 EMPTY2[3];
+ vu8 SR2; /* Status Register 2 */
+ vu8 EMPTY3[3];
+ vu8 CCR; /* Clock Control Register */
+ vu8 EMPTY4[3];
+ vu8 OAR1; /* Own Address Register 1 */
+ vu8 EMPTY5[3];
+ vu8 OAR2; /* Own Address Register 2 */
+ vu8 EMPTY6[3];
+ vu8 DR; /* Data Register */
+ vu8 EMPTY7[3];
+ vu8 ECCR; /* Extended Clock Control Register */
+ vu8 EMPTY8[3];
+} I2C_TypeDef;
+
+/*------------------------------------- VIC ----------------------------------*/
+
+typedef struct
+{
+ vu32 ISR; /* IRQ Status Register */
+ vu32 FSR; /* FIQ Status Register */
+ vu32 RINTSR; /* Raw Interrupt Status Register */
+ vu32 INTSR; /* Interrupt Select Register */
+ vu32 INTER; /* Interrupt Enable Register */
+ vu32 INTECR; /* Interrupt Enable Clear Register */
+ vu32 SWINTR; /* Software Interrupt Register */
+ vu32 SWINTCR; /* Software Interrupt clear Register */
+ vu32 PER; /* Protection Enable Register */
+ vu32 EMPTY1[3];
+ vu32 VAR; /* Vector Address Register */
+ vu32 DVAR; /* Default Vector Address Register */
+ vu32 EMPTY2[50];
+ vu32 VAiR[16]; /* Vector Address 0-15 Register */
+ vu32 EMPTY3[48];
+ vu32 VCiR[16]; /* Vector Control 0-15 Register */
+} VIC_TypeDef;
+
+/*-------------------------------- Motor Control -----------------------------*/
+
+typedef struct
+{
+ vu16 TCPT; /* Tacho Capture Register */
+ vu16 EMPTY1;
+ vu16 TCMP; /* Tacho Compare Register */
+ vu16 EMPTY2;
+ vu16 IPR; /* Input Pending Register */
+ vu16 EMPTY3;
+ vu16 TPRS; /* Tacho Prescaler Register */
+ vu16 EMPTY4;
+ vu16 CPRS; /* PWM Counter Prescaler Register */
+ vu16 EMPTY5;
+ vu16 REP; /* Repetition Counter Register */
+ vu16 EMPTY6;
+ vu16 CMPW; /* Compare Phase W Preload Register */
+ vu16 EMPTY7;
+ vu16 CMPV; /* Compare Phase V Preload Register */
+ vu16 EMPTY8;
+ vu16 CMPU; /* Compare Phase U Preload Register */
+ vu16 EMPTY9;
+ vu16 CMP0; /* Compare 0 Preload Register */
+ vu16 EMPTY10;
+ vu16 PCR0; /* Peripheral Control Register 0 */
+ vu16 EMPTY11;
+ vu16 PCR1; /* Peripheral Control Register 1 */
+ vu16 EMPTY12;
+ vu16 PCR2; /* Peripheral Control Register 2 */
+ vu16 EMPTY13;
+ vu16 PSR; /* Polarity Selection Register */
+ vu16 EMPTY14;
+ vu16 OPR; /* Output Peripheral Register */
+ vu16 EMPTY15;
+ vu16 IMR; /* Interrupt Mask Register */
+ vu16 EMPTY16;
+ vu16 DTG; /* Dead Time Generator Register */
+ vu16 EMPTY17;
+ vu16 ESC; /* Emergency Stop Clear Register */
+ vu16 EMPTY18;
+}MC_TypeDef;
+
+/*------------------------------------- RTC ----------------------------------*/
+
+typedef struct
+{
+ vu32 TR; /* Time Register */
+ vu32 DTR; /* Date Register */
+ vu32 ATR; /* Alarm time Register */
+ vu32 CR; /* Control Register */
+ vu32 SR; /* Status Register */
+ vu32 MILR; /* Millisec Register */
+}RTC_TypeDef;
+
+/*------------------------------------- SSP ----------------------------------*/
+
+typedef struct
+{
+ vu16 CR0; /* Control Register 1 */
+ vu16 EMPTY1;
+ vu16 CR1; /* Control Register 2 */
+ vu16 EMPTY2;
+ vu16 DR; /* Data Register */
+ vu16 EMPTY3;
+ vu16 SR; /* Status Register */
+ vu16 EMPTY4;
+ vu16 PR; /* Clock Prescale Register */
+ vu16 EMPTY5;
+ vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
+ vu16 EMPTY6;
+ vu16 RISR; /* Raw Interrupt Status Register */
+ vu16 EMPTY7;
+ vu16 MISR; /* Masked Interrupt Status Register */
+ vu16 EMPTY8;
+ vu16 ICR; /* Interrupt Clear Register */
+ vu16 EMPTY9;
+ vu16 DMACR; /* DMA Control Register */
+ vu16 EMPTY10;
+}SSP_TypeDef;
+
+/*------------------------------------ UART ----------------------------------*/
+
+typedef struct
+{
+ vu16 DR; /* Data Register */
+ vu16 EMPTY1;
+ vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
+ vu16 EMPTY2[9];
+ vu16 FR; /* Flag Register */
+ vu16 EMPTY3[3];
+ vu16 ILPR; /* IrDA Low-Power counter Register */
+ vu16 EMPTY4;
+ vu16 IBRD; /* Integer Baud Rate Divisor Register */
+ vu16 EMPTY5;
+ vu16 FBRD; /* Fractional Baud Rate Divisor Register */
+ vu16 EMPTY6;
+ vu16 LCR; /* Line Control Register, High byte */
+ vu16 EMPTY7;
+ vu16 CR; /* Control Register */
+ vu16 EMPTY8;
+ vu16 IFLS; /* Interrupt FIFO Level Select Register */
+ vu16 EMPTY9;
+ vu16 IMSC; /* Interrupt Mask Set/Clear Register */
+ vu16 EMPTY10;
+ vu16 RIS; /* Raw Interrupt Status Register */
+ vu16 EMPTY11;
+ vu16 MIS; /* Masked Interrupt Status Register */
+ vu16 EMPTY12;
+ vu16 ICR; /* Interrupt Clear Register */
+ vu16 EMPTY13;
+ vu16 DMACR; /* DMA Control Register */
+ vu16 EMPTY14;
+}UART_TypeDef;
+
+/*------------------------------- Wake-up System -----------------------------*/
+
+typedef struct
+{
+ vu32 CTRL; /* Control Register */
+ vu32 MR; /* Mask Register */
+ vu32 TR; /* Trigger Register */
+ vu32 PR; /* Pending Register */
+ vu32 INTR; /* Software Interrupt Register */
+} WIU_TypeDef;
+
+/*------------------------------- WatchDog Timer -----------------------------*/
+
+typedef struct
+{
+ vu16 CR; /* Control Register */
+ vu16 EMPTY1;
+ vu16 PR; /* Presclar Register */
+ vu16 EMPTY2;
+ vu16 VR; /* Pre-load Value Register */
+ vu16 EMPTY3;
+ vu16 CNT; /* Counter Register */
+ vu16 EMPTY4;
+ vu16 SR; /* Status Register */
+ vu16 EMPTY5;
+ vu16 MR; /* Mask Register */
+ vu16 EMPTY6;
+ vu16 KR; /* Key Register */
+ vu16 EMPTY7;
+} WDG_TypeDef;
+
+/*******************************************************************************
+* Memory Mapping of STR91x *
+*******************************************************************************/
+
+#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
+#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
+
+#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
+#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
+
+#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
+#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
+
+#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
+#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
+
+#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
+#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
+
+#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
+#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
+
+#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
+#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
+
+#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
+#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
+
+/*******************************************************************************
+* Addresses related to the VICs' peripherals *
+*******************************************************************************/
+
+#define VIC0_BASE (AHB_VIC0_U)
+#define VIC1_BASE (AHB_VIC1_U)
+
+/*******************************************************************************
+* Addresses related to the EMI banks *
+*******************************************************************************/
+
+#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
+#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
+#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
+#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
+
+/*******************************************************************************
+* Addresses related to the DMA peripheral *
+*******************************************************************************/
+
+#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
+#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
+#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
+#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
+#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
+#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
+#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
+#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
+
+/*******************************************************************************
+* Addresses related to the APB0 sub-system *
+*******************************************************************************/
+
+#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
+#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
+#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
+#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
+#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
+#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
+#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
+#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
+#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
+#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
+#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
+#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
+#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
+#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
+#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
+
+/*******************************************************************************
+* Addresses related to the APB1 sub-system *
+*******************************************************************************/
+
+#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
+#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
+#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
+#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
+#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
+#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
+#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
+#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
+#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
+#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
+#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
+#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
+#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------- Unbuffered Mode ------------------------------*/
+/*----------------------------------------------------------------------------*/
+
+#ifndef Buffered
+
+/*******************************************************************************
+* AHBAPB peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
+#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
+
+/*******************************************************************************
+* ENET peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define ENET_MAC_BASE (AHB_ENET_MAC_U)
+#define ENET_DMA_BASE (AHB_ENET_DMA_U)
+
+/*******************************************************************************
+* DMA peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define DMA_BASE (AHB_DMA_U)
+
+/*******************************************************************************
+* EMI peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define EMI_BASE (AHB_EMI_U)
+
+/*******************************************************************************
+* FMI peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define FMI_BASE (AHB_FMI_U)
+
+
+#else /* Buffered */
+
+/*----------------------------------------------------------------------------*/
+/*------------------------------ Buffered Mode -------------------------------*/
+/*----------------------------------------------------------------------------*/
+
+/*******************************************************************************
+* AHBAPB peripheral Buffered Base Address *
+*******************************************************************************/
+
+#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
+#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
+
+/*******************************************************************************
+* ENET peripheral Unbuffered Base Address *
+*******************************************************************************/
+
+#define ENET_MAC_BASE (AHB_ENET_MAC_B)
+#define ENET_DMA_BASE (AHB_ENET_DMA_B)
+
+/*******************************************************************************
+* DMA peripheral Buffered Base Address *
+*******************************************************************************/
+
+#define DMA_BASE (AHB_DMA_B)
+
+/*******************************************************************************
+* EMI peripheral Buffered Base Address *
+*******************************************************************************/
+
+#define EMI_BASE (AHB_EMI_B)
+
+/*******************************************************************************
+* FMI peripheral Buffered Base Address *
+*******************************************************************************/
+
+#define FMI_BASE (AHB_FMI_B)
+
+#endif /* Buffered */
+
+/*******************************************************************************
+* DMA channels Base Address *
+*******************************************************************************/
+#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
+#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
+#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
+#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
+#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
+#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
+#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
+#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
+
+/*******************************************************************************
+* EMI Banks peripheral Base Address *
+*******************************************************************************/
+
+#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
+#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
+#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
+#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
+
+/*******************************************************************************
+* APB0 Peripherals' Base addresses *
+*******************************************************************************/
+
+#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
+#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
+#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
+#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
+#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
+#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
+#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
+#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
+#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
+#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
+#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
+#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
+#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
+#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
+#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
+
+/*******************************************************************************
+* APB1 Peripherals' Base addresses *
+*******************************************************************************/
+
+#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
+#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
+#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
+#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
+#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
+#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
+#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
+#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
+#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
+#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
+#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
+#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
+#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
+
+/*******************************************************************************
+* IPs' declaration *
+*******************************************************************************/
+
+/*------------------------------ Non Debug Mode ------------------------------*/
+#undef DEBUG
+#ifndef DEBUG
+
+/*********************************** AHBAPB ***********************************/
+
+#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
+#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
+
+/************************************* EMI ************************************/
+
+#define EMI ((EMI_TypeDef *)EMI_BASE)
+
+/************************************* DMA ************************************/
+
+#define DMA ((DMA_TypeDef *)DMA_BASE)
+#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
+#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
+#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
+#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
+#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
+#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
+#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
+#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
+
+/************************************* EMI ************************************/
+
+#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
+#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
+#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
+#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
+
+/************************************* ENET_MAC ************************************/
+
+#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
+
+/************************************* ENET_DMA ************************************/
+
+#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
+
+/************************************* FMI ************************************/
+
+#define FMI ((FMI_TypeDef *)FMI_BASE)
+
+/************************************* VIC ************************************/
+
+#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
+#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
+
+/*******************************************************************************
+* APB0 Peripherals' *
+*******************************************************************************/
+#define WIU ((WIU_TypeDef *)WIU_BASE)
+#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
+#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
+#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
+#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
+#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
+#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
+#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
+#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
+#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
+#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
+/*******************************************************************************
+* APB1 Peripherals' *
+*******************************************************************************/
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define SCU ((SCU_TypeDef *)SCU_BASE)
+#define MC ((MC_TypeDef *)MC_BASE)
+#define UART0 ((UART_TypeDef *)UART0_BASE)
+#define UART1 ((UART_TypeDef *)UART1_BASE)
+#define UART2 ((UART_TypeDef *)UART2_BASE)
+#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
+#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
+#define CAN ((CAN_TypeDef *)CAN_BASE)
+#define ADC ((ADC_TypeDef *)ADC_BASE)
+#define WDG ((WDG_TypeDef *)WDG_BASE)
+#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
+#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
+
+#else /* DEBUG */
+
+/*-------------------------------- Debug Mode --------------------------------*/
+
+EXT AHBAPB_TypeDef *AHBAPB0;
+EXT AHBAPB_TypeDef *AHBAPB1;
+EXT DMA_TypeDef *DMA;
+EXT DMA_Channel_TypeDef *DMA_Channel0;
+EXT DMA_Channel_TypeDef *DMA_Channel1;
+EXT DMA_Channel_TypeDef *DMA_Channel2;
+EXT DMA_Channel_TypeDef *DMA_Channel3;
+EXT DMA_Channel_TypeDef *DMA_Channel4;
+EXT DMA_Channel_TypeDef *DMA_Channel5;
+EXT DMA_Channel_TypeDef *DMA_Channel6;
+EXT DMA_Channel_TypeDef *DMA_Channel7;
+EXT EMI_Bank_TypeDef *EMI_Bank0;
+EXT EMI_Bank_TypeDef *EMI_Bank1;
+EXT EMI_Bank_TypeDef *EMI_Bank2;
+EXT EMI_Bank_TypeDef *EMI_Bank3;
+EXT FMI_TypeDef *FMI;
+EXT VIC_TypeDef *VIC0;
+EXT VIC_TypeDef *VIC1;
+EXT WIU_TypeDef *WIU;
+EXT TIM_TypeDef *TIM0;
+EXT TIM_TypeDef *TIM1;
+EXT TIM_TypeDef *TIM2;
+EXT TIM_TypeDef *TIM3;
+EXT GPIO_TypeDef *GPIO0;
+EXT GPIO_TypeDef *GPIO1;
+EXT GPIO_TypeDef *GPIO2;
+EXT GPIO_TypeDef *GPIO3;
+EXT GPIO_TypeDef *GPIO4;
+EXT GPIO_TypeDef *GPIO5;
+EXT GPIO_TypeDef *GPIO6;
+EXT GPIO_TypeDef *GPIO7;
+EXT GPIO_TypeDef *GPIO8;
+EXT GPIO_TypeDef *GPIO9;
+EXT RTC_TypeDef *RTC;
+EXT SCU_TypeDef *SCU;
+EXT MC_TypeDef *MC;
+EXT UART_TypeDef *UART0;
+EXT UART_TypeDef *UART1;
+EXT UART_TypeDef *UART2;
+EXT SSP_TypeDef *SSP0;
+EXT SSP_TypeDef *SSP1;
+EXT CAN_TypeDef *CAN;
+EXT ADC_TypeDef *ADC;
+EXT WDG_TypeDef *WDG;
+EXT I2C_TypeDef *I2C0;
+EXT I2C_TypeDef *I2C1;
+EXT ENET_MAC_TypeDef *ENET_MAC;
+EXT ENET_DMA_TypeDef *ENET_DMA;
+
+
+#endif /* DEBUG */
+
+#endif /* __91x_MAP_H*/
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
+
diff --git a/uc_str912/prj_test_lcd/include/91x_scu.h b/uc_str912/prj_test_lcd/include/91x_scu.h new file mode 100644 index 0000000..b9d04f5 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_scu.h @@ -0,0 +1,196 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_scu.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides the SCU library software functions
+* prototypes & definitions
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __91x_SCU_H
+#define __91x_SCU_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_map.h"
+
+/* Exported constants --------------------------------------------------------*/
+
+/*MCLK_Source*/
+#define SCU_MCLK_PLL 0x0
+#define SCU_MCLK_RTC 0x1
+#define SCU_MCLK_OSC 0x2
+
+/*RCLK_Divisor*/
+#define SCU_RCLK_Div1 0xFFFFFFE3
+#define SCU_RCLK_Div2 0x4
+#define SCU_RCLK_Div4 0x8
+#define SCU_RCLK_Div8 0xC
+#define SCU_RCLK_Div16 0x10
+#define SCU_RCLK_Div1024 0x14
+
+/*HCLK_Divisor*/
+#define SCU_HCLK_Div1 0xFFFFFF9F
+#define SCU_HCLK_Div2 0x20
+#define SCU_HCLK_Div4 0x40
+
+/*PCLK_Divisor*/
+#define SCU_PCLK_Div1 0xFFFFFE7F
+#define SCU_PCLK_Div2 0x80
+#define SCU_PCLK_Div4 0x100
+#define SCU_PCLK_Div8 0x180
+
+/*FMICLK_Divisor*/
+#define SCU_FMICLK_Div1 0xFFFEFFFF
+#define SCU_FMICLK_Div2 0x10000
+
+/*BRCLK_Divisor*/
+#define SCU_BRCLK_Div1 0xFFFFFDFF
+#define SCU_BRCLK_Div2 0x200
+
+/*TIMCLK_Source*/
+#define SCU_TIMCLK_EXT 0x1
+#define SCU_TIMCLK_INT 0x0
+
+/*TIMx*/
+#define SCU_TIM01 0x0
+#define SCU_TIM23 0x1
+
+
+/*USBCLK_Source*/
+#define SCU_USBCLK_MCLK 0xFFFFF3FF
+#define SCU_USBCLK_MCLK2 0x400
+#define SCU_USBCLK_EXT 0x800
+
+/*SCU_EMIBCLK*/
+#define SCU_EMIBCLK_Div1 0xFFF9FFFF
+#define SCU_EMIBCLK_Div2 0x20000
+
+/*SCU_EMIMODE*/
+#define SCU_EMI_MUX 0xFFFFFFBF
+#define SCU_EMI_DEMUX 0x40
+
+/*SCU_EMIALE_LEN*/
+#define SCU_EMIALE_LEN1 0xFFFFFEFF
+#define SCU_EMIALE_LEN2 0x100
+
+/*SCU_EMIALE_POL*/
+#define SCU_EMIALE_POLLow 0xFFFFFF7F
+#define SCU_EMIALE_POLHigh 0x80
+
+/*UART_IrDA_Mode*/
+#define SCU_UARTMode_IrDA 0x1
+#define SCU_UARTMode_UART 0x0
+
+/*APBPeriph*/
+#define __TIM01 0x1
+#define __TIM23 0x2
+#define __MC 0x4
+#define __UART0 0x8
+#define __UART1 0x10
+#define __UART2 0x20
+#define __I2C0 0x40
+#define __I2C1 0x80
+#define __SSP0 0x100
+#define __SSP1 0x200
+#define __CAN 0x400
+#define __ADC 0x800
+#define __WDG 0x1000
+#define __WIU 0x2000
+#define __GPIO0 0x4000
+#define __GPIO1 0x8000
+#define __GPIO2 0x10000
+#define __GPIO3 0x20000
+#define __GPIO4 0x40000
+#define __GPIO5 0x80000
+#define __GPIO6 0x100000
+#define __GPIO7 0x200000
+#define __GPIO8 0x400000
+#define __GPIO9 0x800000
+#define __RTC 0x1000000
+
+/*AHBPeriph*/
+#define __FMI 0x1
+#define __FPQBC 0x2
+#define __SRAM 0x8
+#define __SRAM_ARBITER 0x10
+#define __VIC 0x20
+#define __EMI 0x40
+#define __EMI_MEM_CLK 0x80
+#define __DMA 0x100
+#define __USB 0x200
+#define __USB48M 0x400
+#define __ENET 0x800
+#define __PFQBC_AHB 0x1000
+
+/*SCU_IT*/
+#define SCU_IT_LVD_RST 0x10
+#define SCU_IT_SRAM_ERROR 0x8
+#define SCU_IT_ACK_PFQBC 0x4
+#define SCU_IT_LOCK_LOST 0x2
+#define SCU_IT_LOCK 0x1
+
+/*SCU_FLAG*/
+#define SCU_FLAG_SRAM_ERROR 0x20
+#define SCU_FLAG_ACK_PFQBC 0x10
+#define SCU_FLAG_LVD_RESET 0x8
+#define SCU_FLAG_WDG_RST 0x4
+#define SCU_FLAG_LOCK_LOST 0x2
+#define SCU_FLAG_LOCK 0x1
+
+
+/* Module private variables --------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
+ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
+ErrorStatus SCU_PLLCmd(FunctionalState NewState);
+void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
+void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
+void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
+void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
+void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
+void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
+void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
+void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
+void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
+void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
+void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
+void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
+void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source);
+void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler);
+void SCU_USBCLKConfig(u32 USBCLK_Source);
+void SCU_PHYCLKConfig(FunctionalState NewState);
+void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
+void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
+void SCU_EMIModeConfig(u32 SCU_EMIMODE);
+void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
+void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
+FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
+void SCU_ClearFlag(u32 SCU_Flag);
+u32 SCU_GetPLLFreqValue(void);
+u32 SCU_GetMCLKFreqValue(void);
+u32 SCU_GetRCLKFreqValue(void);
+u32 SCU_GetHCLKFreqValue(void);
+u32 SCU_GetPCLKFreqValue(void);
+void SCU_WakeUpLineConfig(u8 EXTint);
+void SCU_SpecIntRunModeConfig(FunctionalState NewState);
+void SCU_EnterIdleMode(void);
+void SCU_EnterSleepMode(void);
+void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode);
+void SCU_PFQBCCmd(FunctionalState NewState);
+
+#endif /*__91x_SCU_H*/
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/91x_type.h b/uc_str912/prj_test_lcd/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_type.h
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : It contains common types and constants used in all the
+* peripherals' drivers.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+**********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*********************************************************************************/
+
+#ifndef __91x_type_H
+#define __91x_type_H
+
+ typedef long long u64;
+ typedef unsigned long u32;
+ typedef unsigned short u16;
+ typedef unsigned char u8;
+
+ typedef signed long s32;
+ typedef signed short s16;
+ typedef signed char s8;
+
+ typedef volatile unsigned long vu32;
+ typedef volatile unsigned short vu16;
+ typedef volatile unsigned char vu8;
+
+ typedef volatile signed long vs32;
+ typedef volatile signed short vs16;
+ typedef volatile signed char vs8;
+
+typedef enum { FALSE = 0, TRUE = !FALSE } bool;
+
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
+
+typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#endif /* __91x_type_H */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/char_code.h b/uc_str912/prj_test_lcd/include/char_code.h new file mode 100644 index 0000000..51775e3 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/char_code.h @@ -0,0 +1,79 @@ +#ifndef char_code
+#define char_code
+
+#define A 65
+#define B 66
+#define C 67
+#define D 68
+#define E 69
+#define F 70
+#define G 71
+#define H 72
+#define I 73
+#define J 74
+#define K 75
+#define L 76
+#define M 77
+#define N 78
+#define O 79
+#define P 80
+#define Q 81
+#define R 82
+#define S 83
+#define T 84
+#define U 85
+#define V 86
+#define W 87
+#define X 88
+#define Y 89
+#define Z 90
+
+#define a 97
+#define b 98
+#define c 99
+#define d 100
+#define e 101
+#define f 102
+#define g 103
+#define h 104
+#define i 105
+#define j 106
+#define k 107
+#define l 108
+#define m 109
+#define n 110
+#define o 111
+#define p 112
+#define q 113
+#define r 114
+#define s 115
+#define t 116
+#define u 117
+#define v 118
+#define w 119
+#define x 120
+#define y 121
+#define z 122
+
+/*
+#define . 46
+#define , 44
+#define - 45
+#define ( 40
+#define ) 41
+#define [ 91
+#define ] 93
+#define { 123
+#define } 125
+#define : 58
+#define ; 59
+#define ! 33
+#define % 37
+#define * 42
+#define + 43
+#define = 61
+*/
+
+#define space 32
+
+#endif
diff --git a/uc_str912/prj_test_lcd/include/lcd_lib_91x.h b/uc_str912/prj_test_lcd/include/lcd_lib_91x.h new file mode 100644 index 0000000..bdc4fdb --- /dev/null +++ b/uc_str912/prj_test_lcd/include/lcd_lib_91x.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2007 PROPOX ********************************
+* File Name : lcd_lib_91x.h
+* Author : PROPOX Team
+* Date First Issued : 09/24/2007 : Version 1.0
+* Description : This file provides all the 2x16 LCD functions.
+********************************************************************************
+* History:
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, PROPOX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion ------------------------------------ */
+#ifndef _lcd_lib_91x_H
+#define _lcd_lib_91x_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_lib.h"
+#include "91x_gpio.h"
+
+/* Private Definision */
+#define D7_set GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_SET)
+#define D6_set GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_SET)
+#define D5_set GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_SET)
+#define D4_set GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET)
+
+#define D7_reset GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_RESET)
+#define D6_reset GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_RESET)
+#define D5_reset GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_RESET)
+#define D4_reset GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET)
+
+#define RS_set GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_SET)
+#define E_set GPIO_WriteBit(GPIO8, GPIO_Pin_5, Bit_SET)
+
+#define RS_reset GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_RESET)
+#define E_reset GPIO_WriteBit(GPIO8, GPIO_Pin_5, Bit_RESET)
+
+void delay(int time);
+void LCDinit(void);
+void LCDsendChar(u8 ch);
+void LCDsendCommand(u8 cmd);
+void LCDclr(void);
+void LCDhome(void);
+void LCDstring(u8* data, u8 nBytes);
+void LCDGotoXY(u8 row, u8 column);
+void LCDshiftLeft(u8 right);
+void LCDshiftRight(u8 left);
+void LCDcursorOn(void);
+void LCDcursorOnBlink(void);
+void LCDcursorOFF(void);
+void LCDblank(void);
+void LCDvisible(void);
+void LCDcursorLeft(u8 left);
+void LCDcursorRight(u8 right);
+
+#endif /* _lcd_lib_91x_H */
+
+
+/******************* (C) COPYRIGHT 2007 PROPOX *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/include/vectors.h b/uc_str912/prj_test_lcd/include/vectors.h new file mode 100644 index 0000000..d48e61f --- /dev/null +++ b/uc_str912/prj_test_lcd/include/vectors.h @@ -0,0 +1,67 @@ +/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+#ifndef _VECTOR_H
+#define _VECTOR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Undefined_Handler(void);
+void FIQ_Handler(void);
+void SWI_Handler(void);
+void Prefetch_Handler(void);
+void Abort_Handler(void);
+void WDG_IRQHandler(void);
+void SW_IRQHandler(void);
+void ARMRX_IRQHandler(void);
+void ARMTX_IRQHandler(void);
+void TIM0_IRQHandler(void);
+void TIM1_IRQHandler(void);
+void TIM2_IRQHandler(void);
+void TIM3_IRQHandler(void);
+void USBHP_IRQHandler(void);
+void USBLP_IRQHandler(void);
+void SCU_IRQHandler(void);
+void ENET_IRQHandler(void);
+void DMA_IRQHandler(void);
+void CAN_IRQHandler(void);
+void MC_IRQHandler(void);
+void ADC_IRQHandler(void);
+void UART0_IRQHandler(void);
+void UART1_IRQHandler(void);
+void UART2_IRQHandler(void);
+void I2C0_IRQHandler(void);
+void I2C1_IRQHandler(void);
+void SSP0_IRQHandler(void);
+void SSP1_IRQHandler(void);
+void LVD_IRQHandler(void);
+void RTC_IRQHandler(void);
+void WIU_IRQHandler(void);
+void EXTIT0_IRQHandler(void);
+void EXTIT1_IRQHandler(void);
+void EXTIT2_IRQHandler(void);
+void EXTIT3_IRQHandler(void);
+void USBWU_IRQHandler(void);
+void PFQBC_IRQHandler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_VECTOR_H
diff --git a/uc_str912/prj_test_lcd/load_amontec.gdb b/uc_str912/prj_test_lcd/load_amontec.gdb new file mode 100644 index 0000000..8767ed9 --- /dev/null +++ b/uc_str912/prj_test_lcd/load_amontec.gdb @@ -0,0 +1,15 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +set remote hardware-breakpoint-limit 2 +set remote hardware-watchpoint-limit 2 + +target remote localhost:3333 + +monitor reset init +monitor halt + +load lcd.elf +file lcd.elf diff --git a/uc_str912/prj_test_lcd/load_segger.gdb b/uc_str912/prj_test_lcd/load_segger.gdb new file mode 100644 index 0000000..cd9fd7e --- /dev/null +++ b/uc_str912/prj_test_lcd/load_segger.gdb @@ -0,0 +1,20 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load lcd.elf +file lcd.elf diff --git a/uc_str912/prj_test_lcd/src/lcd.c b/uc_str912/prj_test_lcd/src/lcd.c new file mode 100644 index 0000000..9eae1c1 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/lcd.c @@ -0,0 +1,93 @@ +/******************************************************************************
+ * www.propox.com
+ * MMstr912 - Minimodu³ Ethernetowy z procesorem ARM9 STR912.
+ * Ethernet minimodule with ARM9 STR912 microcontroller.
+ *
+ * LCD Test - wyswietla tekst 'www.propox.com' na LCD
+ * put text 'www.propox.com' on LCD
+ *
+ * P8.0, P8.1, P8.2, P8.3 - D4, D5, D6, D7
+ * P8.4, P8.5 - RS, E
+
+ * Includes ------------------------------------------------------------------*/
+/* Pliki nag³ówkowe ----------------------------------------------------------*/
+/* Library includes. */
+#include "91x_lib.h"
+#include "91x_gpio.h"
+#include "91x_map.h"
+#include "91x_scu.h"
+#include "char_code.h"
+#include "lcd_lib_91x.h"
+
+//#include <targets/STR912FW44.h> rem BLa
+
+/* Hardware Configuration */
+/* Konfiguracja sprzetu */
+void HardwareConf(void)
+{
+ //Main clock as exesternal oscillator 25MHz
+ //G³ówny zegar to kwarc 25MHz
+ SCU_MCLKSourceConfig(SCU_MCLK_OSC);
+ //Disable reset for GPIO8
+ //wylaczenie resetu na GPIO8
+ SCU_APBPeriphReset(__GPIO8, DISABLE);
+ //Enable clock for GPIO8
+ //W³¹czenie zegara na GPIO8
+ SCU_APBPeriphClockConfig(__GPIO8, ENABLE);
+}
+
+
+/* Ports Configuration */
+/* Konfiguracja protow */
+void LCD_DataLinesConfig()
+{
+ /* Private typedef */
+ /* Deklaracja struktury */
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Configure D7~D4 data lines in Output Push-Pull mode */
+ /* Konfiguracja lini portu 8 jako wyjsc D7-D4 w trybie push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
+ GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt1;
+ GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
+ GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
+ GPIO_Init(GPIO8, &GPIO_InitStructure);
+
+}
+
+
+int main()
+{
+u8 web[] = "www.propox.com";
+u8 title[] = "MMstr912";
+
+//Hardware Configuration
+//Konfiguracja sprzetu
+HardwareConf();
+//Ports Configuration
+//Konfiguracja portow
+LCD_DataLinesConfig();
+
+LCDinit();
+LCDcursorOFF();
+LCDGotoXY(0,0);
+LCDstring(web,14);
+delay(250000);
+LCDGotoXY(3,1);
+LCDstring(title,8);
+
+while(1)
+{
+ delay(500000);
+ LCDshiftLeft(1);
+ delay(100000);
+ LCDshiftLeft(1);
+
+ delay(500000);
+ LCDshiftRight(1);
+ delay(100000);
+ LCDshiftRight(1);
+}
+
+return 0;
+}
diff --git a/uc_str912/prj_test_lcd/src/lcd_lib_91x.c b/uc_str912/prj_test_lcd/src/lcd_lib_91x.c new file mode 100644 index 0000000..7c01f53 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/lcd_lib_91x.c @@ -0,0 +1,455 @@ +/******************** (C) COPYRIGHT 2007 PROPOX ********************************
+* File Name : lcd_lib_91x.c
+* Author : PROPOX Team
+* Date First Issued : 09/24/2007 : Version 1.0
+* Description : This file provides all the 2x16 LCD functions.
+********************************************************************************
+* History:
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, PROPOX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_lib.h"
+#include "91x_gpio.h"
+#include "91x_map.h"
+#include "91x_scu.h"
+#include "lcd_lib_91x.h"
+
+
+/*******************************************************************************
+* Function Name : delay
+* Description : Delay (opoznienie)
+*
+* Input : time - number of cycles
+* Output : None
+* Return : None
+*******************************************************************************/
+void delay(int time)
+{
+ while(time--)
+ asm volatile ("nop");
+}
+
+/*******************************************************************************
+* Function Name : LCDinit
+* Description : Inicialize LCD (Inicjalizacja LCD)
+* (4 bit data, 2 lines, characters 5x7, blinking cursor on)
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDinit(void)
+{
+ GPIO_Write(GPIO8, 0x00);
+ delay(375000); //15ms
+ //--------- Write 0x03 -----------
+ D7_reset;
+ D6_reset;
+ D5_set;
+ D4_set;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(125000); //5ms
+ //--------- Write 0x03 -----------
+ D7_reset;
+ D6_reset;
+ D5_set;
+ D4_set;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //--------- Write 0x03 -----------
+ D7_reset;
+ D6_reset;
+ D5_set;
+ D4_set;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //--------- Enable Four Bit Mode ----------
+ D7_reset;
+ D6_reset;
+ D5_set;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //---------- Set Interface Length ----------
+ //Write 0x2 - 4 bits
+ D7_reset;
+ D6_reset;
+ D5_set;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //Write 0x8 - 2 lines, 5x7
+ D7_set;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //---------- Turn off the Display ----------
+ //Write 0x0
+ D7_reset;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //Write 0x8
+ D7_set;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //------------ Clear the Display -----------
+ //Write 0x0
+ D7_reset;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //Write 0x1
+ D7_reset;
+ D6_reset;
+ D5_reset;
+ D4_set;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //-------- Set Cursor Move Direction --------
+ //Write 0x0
+ D7_reset;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //Write 0x6 - Increment the Cursor
+ D7_reset;
+ D6_set;
+ D5_set;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //---------- Enable Display/Cursor ----------
+ //Write 0x0
+ D7_reset;
+ D6_reset;
+ D5_reset;
+ D4_reset;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+ //Write 0xF - Display on, cursor on, blink on
+ D7_set;
+ D6_set;
+ D5_set;
+ D4_set;
+ E_set;
+ delay(25000); //1ms
+ E_reset;
+ delay(25000); //1ms
+}
+
+/*******************************************************************************
+* Function Name : LCDsendChar
+* Description : Send Char to LCD (Wyslanie znaku na LCD)
+*
+* Input : ch - is a ascii code of character or char from char_code.h
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDsendChar(u8 ch)
+{
+ //4 MSB bits
+ //4 starsze bity
+ GPIO_Write(GPIO8, (ch>>4) & 0x0f);
+ RS_set;
+ E_set;
+ delay(25000);
+ E_reset;
+ delay(25000);
+ //4 LSB bits
+ //4 mlodsze bity
+ GPIO_Write(GPIO8, ch & 0x0f);
+ RS_set;
+ E_set;
+ delay(25000);
+ E_reset;
+ delay(25000);
+}
+
+/*******************************************************************************
+* Function Name : LCDsendCommand
+* Description : Send Command to LCD (Wyslanie rozkazu do LCD)
+*
+* Input : cmd - is a ascii code of command
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDsendCommand(u8 cmd)
+{
+ //4 MSB bits
+ //4 starsze bity
+ GPIO_Write(GPIO8, (cmd>>4) & 0x0f);
+ RS_reset;
+ E_set;
+ delay(25000);
+ E_reset;
+ delay(25000);
+ //4 LSB bits
+ //4 mlodsze bity
+ GPIO_Write(GPIO8, cmd & 0x0f);
+ RS_reset;
+ E_set;
+ delay(25000);
+ E_reset;
+ delay(25000);
+}
+
+/*******************************************************************************
+* Function Name : LCDclr
+* Description : Clear LCD (Czyszczenie LCD)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDclr(void)
+{
+ LCDsendCommand(0x01);
+}
+
+/*******************************************************************************
+* Function Name : LCDhome
+* Description : LCD cursor home (Przesuniecie kursora na pozycje poczatkowa)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDhome(void)
+{
+ LCDsendCommand(0x02);
+}
+
+/*******************************************************************************
+* Function Name : LCDstring
+* Description : Outputs string to LCD (Wyswietl ciag znakow na LCD)
+*
+* Input : data - pointer to start of table, nBytes - nuber of bytes to send
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDstring(u8* data, u8 nBytes)
+{
+ u8 count;
+ //check to make sure we have a good pointer
+ //sprawdzenie zgodnosci wskaznika
+ if (!data) return;
+
+ //print data
+ //wyswietl znaki
+ for(count=0; count<nBytes; count++)
+ {
+ LCDsendChar(data[count]);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCDGotoXY
+* Description : Cursor to X Y position (Kursor na pozycje XY)
+*
+* Input : row - x position, column - y position
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDGotoXY(u8 row, u8 column)
+{
+#define LCD_DDRAM 7
+
+#define LCD_LINE0_DDRAMADDR 0x00
+#define LCD_LINE1_DDRAMADDR 0x40
+#define LCD_LINE2_DDRAMADDR 0x14
+#define LCD_LINE3_DDRAMADDR 0x54
+
+ u8 DDRAMAddr;
+ //remap lines into proper order
+ //wyznaczenie adresu polozenia
+ switch(column)
+ {
+ case 0: DDRAMAddr = LCD_LINE0_DDRAMADDR + row; break;
+ case 1: DDRAMAddr = LCD_LINE1_DDRAMADDR + row; break;
+ case 2: DDRAMAddr = LCD_LINE2_DDRAMADDR + row; break;
+ case 3: DDRAMAddr = LCD_LINE3_DDRAMADDR + row; break;
+ default: DDRAMAddr = LCD_LINE0_DDRAMADDR + row;
+ }
+ //set data address
+ //wyslanie adresu
+ LCDsendCommand(1<<LCD_DDRAM | DDRAMAddr);
+}
+
+/*******************************************************************************
+* Function Name : LCDshiftLeft
+* Description : Scrol n of characters Right (Przsuniecie znakow o n w prawo)
+*
+* Input : right - number of characters
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDshiftLeft(u8 right)
+{
+u8 count;
+ for (count=0;count<right;count++)
+ {
+ LCDsendCommand(0x1E);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCDshiftRight
+* Description : Scrol n of characters Left (Przsuniecie znakow o n w lewo)
+*
+* Input : left - number of characters
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDshiftRight(u8 left)
+{
+u8 count;
+ for (count=0;count<left;count++)
+ {
+ LCDsendCommand(0x18);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCDcursorOn
+* Description : Displays LCD cursor (Kursor aktywny)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDcursorOn(void)
+{
+ LCDsendCommand(0x0E);
+}
+
+/*******************************************************************************
+* Function Name : LCDcursorOnBlink
+* Description : Displays LCD blinking cursor (Migajacy kursor aktywny)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDcursorOnBlink(void)
+{
+ LCDsendCommand(0x0F);
+}
+
+/*******************************************************************************
+* Function Name : LCDcursorOFF
+* Description : Turns OFF cursor (Kursor wylaczony)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDcursorOFF(void)
+{
+ LCDsendCommand(0x0C);
+}
+
+/*******************************************************************************
+* Function Name : LCDblank
+* Description : Blanks LCD (LCD nieaktywny)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDblank(void)
+{
+ LCDsendCommand(0x08);
+}
+
+/*******************************************************************************
+* Function Name : LCDvisible
+* Description : Shows LCD (LCD aktywny)
+*
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDvisible(void)
+{
+ LCDsendCommand(0x0C);
+}
+
+/*******************************************************************************
+* Function Name : LCDcursorLeft
+* Description : Moves cursor by n poisitions left (Kursor n pozycji w lewo)
+*
+* Input : left - number of positions
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDcursorLeft(u8 left)
+{
+u8 count;
+ for (count=0;count<left;count++)
+ {
+ LCDsendCommand(0x10);
+ }
+}
+
+/*******************************************************************************
+* Function Name : LCDcursorRight
+* Description : Moves cursor by n poisitions right (Kursor n pozycji w prawo)
+*
+* Input : right - number of positions
+* Output : None
+* Return : None
+*******************************************************************************/
+void LCDcursorRight(u8 right)
+{
+u8 count;
+ for (count=0;count<right;count++)
+ {
+ LCDsendCommand(0x14);
+ }
+}
+
+/******************* (C) COPYRIGHT 2007 PROPOX *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/src/startup.s b/uc_str912/prj_test_lcd/src/startup.s new file mode 100644 index 0000000..cef54d8 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/startup.s @@ -0,0 +1,233 @@ +/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+/**** Startup Code (executed after Reset) ****/
+
+/* Frequency values kHz */
+/* set to suit target hardware */
+
+ .equ FOSC, 25000
+
+/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+
+ .equ Mode_USR, 0x10
+ .equ Mode_FIQ, 0x11
+ .equ Mode_IRQ, 0x12
+ .equ Mode_SVC, 0x13
+ .equ Mode_ABT, 0x17
+ .equ Mode_UND, 0x1B
+ .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
+
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
+
+ .equ SRAM32, 0x00
+ .equ SRAM64, 0x08
+ .equ SRAM96, 0x10
+
+/* --- System memory locations */
+
+ .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */
+
+ .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */
+ .equ BBSR_off_addr, 0x00
+ .equ NBBSR_off_addr, 0x04
+ .equ BBADR_off_addr, 0x0C
+ .equ NBBADR_off_addr, 0x10
+ .equ CR_off_addr, 0x18
+
+.ifndef LIBUFF
+ .equ LIBUFF, 0
+.endif
+
+/* Startup Code must be linked first at Address at which it expects to run. */
+
+ .text
+ .arm
+ .section .init, "ax"
+
+ .global _start
+ .global _Main_Crystal
+
+/* After remap this will be our reset handler */
+
+_start:
+ LDR pc, =NextInst
+NextInst:
+
+ NOP /* Wait for OSC stabilization */
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+/* Enable buffered mode */
+
+.if LIBUFF
+ MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */
+ ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */
+ MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */
+.endif
+
+/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */
+/* when the bank 0 is the boot bank, then enable the Bank 1. */
+
+ LDR r0, =FMI_BASE_UMB
+ LDR r1, =0x4 /* configure 512KB Boot bank 0 */
+ STR r1, [r0, #BBSR_off_addr]
+
+ LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */
+ STR r1, [r0, #NBBSR_off_addr]
+
+ LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */
+ STR r1, [r0, #BBADR_off_addr]
+
+ LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */
+ STR r1, [r0, #NBBADR_off_addr]
+
+ LDR r1, =0x18 /* Flash Banks 0 1 enabled */
+ STR r1, [r0, #CR_off_addr]
+
+/* Enable 96K RAM */
+
+ LDR r0, =SCRO_AHB_UMB
+# LDR r1, =0x0196 /* prefetch disabled, default enabled */
+ LDR r1, =0x0187|SRAM96
+ STR r1, [r0]
+
+/* Set bits 17-18 (Instruction/Data TCM order) of the */
+/* Core Configuration Control Register */
+
+ MOV r0, #0x60000
+ MCR p15, 0x1, r0, c15, c1, 0
+
+/* Setup Stack for each mode */
+
+/* Enter Abort Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit
+ LDR sp, =__stack_abt_end__
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_UND|I_Bit|F_Bit
+ LDR sp, =__stack_und_end__
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit
+ LDR sp, =__stack_svc_end__
+
+/* Enter FIQ Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+ LDR sp, =__stack_fiq_end__
+
+/* Enter IRQ Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+ LDR sp, =__stack_irq_end__
+
+/* Enter System/User Mode and set its Stack Pointer */
+
+ MSR cpsr_c, #Mode_SYS
+ LDR sp, =__stack_end__
+
+/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */
+
+ LDR sl, =__bss_end__
+
+/* Relocate .data section (Copy from ROM to RAM) */
+
+ LDR r1, =_etext
+ LDR r2, =__data_start
+ LDR r3, =_edata
+LoopRel:
+ CMP r2, r3
+ LDRLO r0, [r1], #4
+ STRLO r0, [r2], #4
+ BLO LoopRel
+
+/* Clear .bss section (Zero init) */
+
+ MOV r0, #0
+ LDR r1, =__bss_start__
+ LDR r2, =__bss_end__
+LoopZI:
+ CMP r1, r2
+ STRLO r0, [r1], #4
+ BLO LoopZI
+
+/* Call C++ constructors */
+
+ LDR r0, =__ctors_start__
+ LDR r1, =__ctors_end__
+ctor_loop:
+ CMP r0, r1
+ BEQ ctor_end
+ LDR r2, [r0], #4
+ STMFD sp!, {r0-r1}
+ BLX r2
+ LDMFD sp!, {r0-r1}
+ B ctor_loop
+ctor_end:
+
+/* Need to set up standard file handles */
+/* Only used under simulator, normally overide syscall.c */
+
+# BL initialise_monitor_handles
+
+/* if we use debug version of str9lib this will call the init function */
+
+ BL libdebug
+libdebug:
+
+/* Enter the C code, use B instruction so as to never return */
+/* use BL main if you want to use c++ destructors below */
+
+ B main
+
+/* Call destructors */
+
+# LDR r0, =__dtors_start__
+# LDR r1, =__dtors_end__
+#dtor_loop:
+# CMP r0, r1
+# BEQ dtor_end
+# LDR r2, [r0], #4
+# STMFD sp!, {r0-r1}
+# BLX r2
+# LDMFD sp!, {r0-r1}
+# B dtor_loop
+#dtor_end:
+
+/* Return from main, loop forever. */
+
+#exit_loop:
+# B exit_loop
+
+/* Fosc values, used by libstr9 */
+
+_Main_Crystal: .long FOSC
+
+ .weak libdebug
+
+ .end
diff --git a/uc_str912/prj_test_lcd/src/vector.s b/uc_str912/prj_test_lcd/src/vector.s new file mode 100644 index 0000000..7708f54 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/vector.s @@ -0,0 +1,202 @@ +/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+ .equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */
+ .equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */
+
+ .equ Mode_USR, 0x10
+ .equ Mode_FIQ, 0x11
+ .equ Mode_IRQ, 0x12
+ .equ Mode_SVC, 0x13
+ .equ Mode_ABT, 0x17
+ .equ Mode_UND, 0x1B
+ .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
+
+ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
+ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
+
+ .text
+ .arm
+ .section .vectors, "ax"
+
+ .global Reset_Vec
+
+/* Note: LDR PC instructions are used here, though branch (B) instructions */
+/* could also be used, unless the ROM is at an address >32MB. */
+
+/*******************************************************************************
+ Exception vectors
+*******************************************************************************/
+
+Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */
+Undef_Vec: LDR pc, Undefined_Addr
+SWI_Vec: LDR pc, SWI_Addr
+PAbt_Vec: LDR pc, Prefetch_Addr
+DAbt_Vec: LDR pc, Abort_Addr
+ NOP /* Reserved vector */
+IRQ_Vec: LDR pc, IRQ_Addr
+FIQ_Vec: LDR pc, FIQ_Addr
+
+/*******************************************************************************
+ Exception handlers address table
+*******************************************************************************/
+
+Reset_Addr: .word _start
+Undefined_Addr: .word UndefinedHandler
+SWI_Addr: .word SWIHandler
+Prefetch_Addr: .word PrefetchHandler
+Abort_Addr: .word AbortHandler
+ .word 0 /* reserved */
+IRQ_Addr: .word IRQHandler
+FIQ_Addr: .word FIQHandler
+
+/*******************************************************************************
+ Exception Handlers
+*******************************************************************************/
+
+/*******************************************************************************
+* Macro Name : SaveContext
+* Description : This macro used to save the context before entering
+ an exception handler.
+* Input : The range of registers to store.
+* Output : none
+*******************************************************************************/
+
+.macro SaveContext reg1 reg2
+ STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */
+ /* address lr_ mode into the stack */
+ MRS r1, spsr /* Save the spsr_mode into r1 */
+ STMFD sp!, {r1} /* Save spsr */
+.endm
+
+/*******************************************************************************
+* Macro Name : RestoreContext
+* Description : This macro used to restore the context to return from
+ an exception handler and continue the program execution.
+* Input : The range of registers to restore.
+* Output : none
+*******************************************************************************/
+
+.macro RestoreContext reg1 reg2
+ LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */
+ MSR spsr_cxsf, r1 /* Restore spsr_mode */
+ LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */
+ /* the exception interrupt */
+.endm
+
+/*******************************************************************************
+* Function Name : IRQHandler
+* Description : This function called when IRQ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+IRQHandler:
+ SUB lr, lr, #4 /* Update the link register */
+ SaveContext r0, r12 /* Save the workspace plus the current */
+ /* return address lr_irq and spsr_irq */
+ LDR r0, =VectorAddress
+ LDR r0, [r0] /* Read the routine address */
+ LDR r1, =VectorAddressDaisy
+ LDR r1, [r1]
+ /* Padding between the acknowledge and re-enable of interrupts */
+ /* For more details, please refer to the following URL */
+ /* http://www.arm.com/support/faqip/3682.html */
+ NOP
+ NOP
+ MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */
+ STMFD sp!, {lr} /* Save the link register. */
+ LDR lr, =ReturnAddress /* Read the return address. */
+ MOV pc, r0 /* Branch to the IRQ handler. */
+ReturnAddress:
+ LDMFD sp!, {lr} /* Restore the link register. */
+ MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit /* Switch to IRQ mode and disable IRQ */
+ LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */
+ STR r0, [r0] /* respective interrupt in the internal interrupt */
+ LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */
+ STR r1, [r1] /* respective interrupt in the internal interrupt */
+ RestoreContext r0, r12 /* Restore the context and return to the program execution. */
+
+/*******************************************************************************
+* Function Name : SWIHandler
+* Description : This function called when SWI instruction executed.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+SWIHandler:
+ SaveContext r0, r12 /* r0 holds swi number */
+ MOV r1, sp /* load regs */
+ BL SWI_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : UndefinedHandler
+* Description : This function called when undefined instruction
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+UndefinedHandler:
+ SaveContext r0, r12
+ BL Undefined_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : PrefetchAbortHandler
+* Description : This function called when Prefetch Abort
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+PrefetchHandler:
+ SUB lr, lr, #4 /* Update the link register. */
+ SaveContext r0, r12
+ BL Prefetch_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : DataAbortHandler
+* Description : This function is called when Data Abort
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+AbortHandler:
+ SUB lr, lr, #8 /* Update the link register. */
+ SaveContext r0, r12
+ BL Abort_Handler
+ RestoreContext r0, r12
+
+/*******************************************************************************
+* Function Name : FIQHandler
+* Description : This function is called when FIQ
+ exception is entered.
+* Input : none
+* Output : none
+*******************************************************************************/
+
+FIQHandler:
+ SUB lr, lr, #4 /* Update the link register. */
+ SaveContext r0, r7
+ BL FIQ_Handler
+ RestoreContext r0, r7
+
+ .end
diff --git a/uc_str912/prj_test_lcd/src/vectors.c b/uc_str912/prj_test_lcd/src/vectors.c new file mode 100644 index 0000000..4022391 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/vectors.c @@ -0,0 +1,462 @@ +/***********************************************************************************
+* Copyright 2005 Anglia Design
+* This demo code and associated components are provided as is and has no warranty,
+* implied or otherwise. You are free to use/modify any of the provided
+* code at your own risk in your applications with the expressed limitation
+* of liability (see below)
+*
+* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
+* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
+* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+*
+* Author : Spencer Oliver
+* Web : www.anglia-designs.com
+*
+***********************************************************************************/
+
+#include "vectors.h"
+
+/*******************************************************************************
+* Function Name : Undefined_Handler
+* Description : This function Undefined instruction exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void Undefined_Handler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : SWI_Handler
+* Description : This function handles SW exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SWI_Handler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : Prefetch_Handler
+* Description : This function handles preftetch abort exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void Prefetch_Handler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : Abort_Handler
+* Description : This function handles data abort exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void Abort_Handler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : FIQ_Handler
+* Description : This function handles FIQ exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void FIQ_Handler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : WDG_IRQHandler
+* Description : This function handles the WDG interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WDG_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : SW_IRQHandler
+* Description : This function handles the SW interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SW_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : ARMRX_IRQHandler
+* Description : This function handles the ARMRX interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ARMRX_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : ARMTX_IRQHandler
+* Description : This function handles the ARMTX interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ARMTX_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : TIM0_IRQHandler
+* Description : This function handles the TIM0 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM0_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : TIM1_IRQHandler
+* Description : This function handles the TIM1 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : TIM2_IRQHandler
+* Description : This function handles the TIM2 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM2_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : TIM3_IRQHandler
+* Description : This function handles the TIM3 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM3_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : USBHP_IRQHandler
+* Description : This function handles the USBHP interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USBHP_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : USBLP_IRQHandler
+* Description : This function handles the USBLP interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USBLP_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : SCU_IRQHandler
+* Description : This function handles the SCU interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : ENET_IRQHandler
+* Description : This function handles the ENET interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ENET_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : DMA_IRQHandler
+* Description : This function handles the DMA interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : CAN_IRQHandler
+* Description : This function handles the CAN interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void CAN_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : MC_IRQHandler
+* Description : This function handles the MC interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void MC_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : ADC_IRQHandler
+* Description : This function handles the ADC interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : UART0_IRQHandler
+* Description : This function handles the UART0 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UART0_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : UART1_IRQHandler
+* Description : This function handles the UART1 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UART1_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : UART2_IRQHandler
+* Description : This function handles the UART2 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UART2_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : I2C0_IRQHandler
+* Description : This function handles the I2C0 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C0_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : I2C1_IRQHandler
+* Description : This function handles the I2C1 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C1_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : SSP0_IRQHandler
+* Description : This function handles the SSP0 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SSP0_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : SSP1_IRQHandler
+* Description : This function handles the SSP1 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SSP1_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : LVD_IRQHandler
+* Description : This function handles the LVD interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void LVD_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : RTC_IRQHandler
+* Description : This function handles the RTC interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : WIU_IRQHandler
+* Description : This function handles the WIU interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WIU_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : EXTIT0_IRQHandler
+* Description : This function handles the EXTIT0 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTIT0_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : EXTIT1_IRQHandler
+* Description : This function handles the EXTIT1 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTIT1_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : EXTIT2_IRQHandler
+* Description : This function handles the EXTIT2 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTIT2_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : EXTIT3_IRQHandler
+* Description : This function handles the EXTIT3 interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTIT3_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : USBWU_IRQHandler
+* Description : This function handles the USBWU interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USBWU_IRQHandler(void)
+{
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name : PFQBC_IRQHandler
+* Description : This function handles the PFQBC interrupt request
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void PFQBC_IRQHandler(void)
+{
+ while(1);
+}
diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c b/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_ahbapb.c
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides all the AHBAPB software functions.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_ahbapb.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF
+#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0
+#define AHBAPB_Address_Mask 0xFEFFFFFF
+#define AHBAPB_FLAG_RW_Mask 0x01000000
+/*******************************************************************************
+* Function Name : AHBAPB_DeInit
+* Description : Deinitializes the AHBAPBx peripheral registers to their default
+* reset values.
+* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx)
+{
+ AHBAPBx->BCR = 0x00000000;
+ AHBAPBx->BSR = 0x00000000;
+}
+/*******************************************************************************
+* Function Name : AHBAPB_Init
+* Description : Initializes the AHBAPBx peripheral according to the specified
+* parameters in the AHBAPB_InitStruct .
+* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral.
+* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that
+* contains the configuration information for the specified AHBAPB
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct)
+{
+
+ if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable)
+ {
+ /* Set SPLITEN bit;*/
+ AHBAPBx->BCR |= AHBAPB_Split_Enable;
+ /*Split_CNT bits[20:16]*/
+ AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask;
+ AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16;
+ }
+ else
+ {
+ /*/ Clear SPLITEN bit;*/
+ AHBAPBx->BCR &= AHBAPB_Split_Disable;
+ }
+ /*APB Time out*/
+ if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable)
+ {
+ /* Set ERREN bit*/
+ AHBAPBx->BCR |= AHBAPB_Error_Enable;
+ /*Time ouit counter*/
+ AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask;
+ AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut;
+ }
+ else
+ {
+ /* Clear ERREN bit*/
+ AHBAPBx->BCR &= AHBAPB_Error_Disable;
+ }
+}
+
+/*******************************************************************************
+* Function Name : AHBAPB_StructInit
+* Description : Initialize the AHBAPB Init Structure parameters
+* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct)
+{
+ /* Reset AHBAPB init structure parameters values */
+ AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable;
+ AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF;
+ AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable;
+ AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF;
+
+}
+
+/*******************************************************************************
+* Function Name : AHBAPB_GetFlagStatus
+* Description : Checks whether the specified AHBAPB flag is set or not.
+* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral
+* - AHBAPB_FLAG: specifies the flag to check.
+* This parameter can be one of the following values:
+* - AHBAPB_FLAG_ERROR: error flag
+* - AHBAPB_FLAG_OUTM : Out of Memory flag
+* - AHBAPB_FLAG_APBT : APB Time-out flag
+* - AHBAPB_FLAG_RW : Access type flag
+* Output : None
+* Return : The new state of AHBAPB_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG)
+{
+ if(AHBAPB_FLAG == AHBAPB_FLAG_RW)
+ {
+ if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET)
+ {
+ return RESET;
+ }
+ else
+ {
+ return SET;
+ }
+ }
+ else
+ {
+ if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET)
+ {
+ return RESET;
+ }
+ else
+ {
+ return SET;
+ }
+ }
+}
+/*******************************************************************************
+* Function Name : AHBAPB_ClearFlag
+* Description : Clears the AHBAPBx flags.
+* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral
+* - AHBAPB_FLAG: flags to clear. This parameter one of the
+* following values:
+* - AHBAPB_FLAG_ERROR: error flag
+* - AHBAPB_FLAG_OUTM : Out of Memory flag
+* - AHBAPB_FLAG_APBT : APB Time-out flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG)
+{
+ /* Clear the flag */
+ AHBAPBx->BSR &= AHBAPB_FLAG;
+}
+/*******************************************************************************
+* Function Name : AHBAPB_GetPeriphAddrError
+* Description : Gets the AHBAPB error address peripherals.
+* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral
+* Output : None
+* Return : The Peropheral address error
+*******************************************************************************/
+u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx)
+{
+ u32 AHBAPB_Address = 0x00000000;
+
+ /*Return Oeripheral address without RW bit*/
+ AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask;
+ return (AHBAPB_Address);
+}
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c b/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_fmi.c
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides all the FMI software functions.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+
+/* Standard include ----------------------------------------------------------*/
+#include "91x_fmi.h"
+
+/* Include of other module interface headers ---------------------------------*/
+/* Local includes ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define TIMEOUT 0xFFFFFF /* Timeout value */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Interface functions -------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/*******************************************************************************
+* Function Name : FMI_BankRemapConfig
+* Description : Configure the addresses and sizes of bank 0 and bank 1.
+* Input1 : FMI_BootBankSize: specifies the boot bank size.
+* This parameter can be one of the following values:
+* - 0x0: 32KBytes.
+* - 0x1: 64KBytes.
+* - 0x2: 128KBytes.
+* - 0x3: 256KBytes.
+* - 0x4: 512KBytes.
+* ....
+* - 0xB: 64MBytes.
+* Input2 : FMI_NonBootBankSize: specifies the non boot bank size.
+* This parameter can be one of the following values:
+* - 0x0: 8KBytes.
+* - 0x1: 16KBytes.
+* - 0x2: 32KBytes.
+* - 0x3: 64KBytes.
+* ....
+* - 0xD: 64MBytes.
+* Input3 : FMI_BootBankAddress: specifies the address of the boot bank.
+* Input4 : FMI_NonBootBankAddress: specifies the address of the non
+* boot bank.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
+ u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress)
+{
+ FMI->BBSR = FMI_BootBankSize;
+ FMI->NBBSR = FMI_NonBootBankSize;
+ FMI->BBADR = (FMI_BootBankAddress >> 2);
+ FMI->NBBADR = (FMI_NonBootBankAddress >> 2);
+ FMI->CR |= 0x18; /* Enable bank 1 */
+}
+
+/*******************************************************************************
+* Function Name : FMI_Config
+* Description : Configure the FMI.
+* Input1 : FMI_ReadWaitState: specifies the needed read wait states.
+* This parameter can be one of the following values:
+* - FMI_READ_WAIT_STATE_1: One read wait state.
+* - FMI_READ_WAIT_STATE_2: Two read wait states.
+* - FMI_READ_WAIT_STATE_3: Three read wait states.
+* Input2 : FMI_WriteWaitState: specifies the needed write wait states.
+* This parameter can be one of the following values:
+* - FMI_WRITE_WAIT_STATE_1: One write wait state.
+* - FMI_WRITE_WAIT_STATE_2: Two write wait states.
+* Input3 : FMI_PWD: specifies the power down mode status.
+* This parameter can be one of the following values:
+* - FMI_PWD_ENABLE: Enable the PWD.
+* - FMI_PWD_DISABLE: Disable the PWD.
+* Input4 : FMI_LVDEN: specifies the low voltage detector status.
+* This parameter can be one of the following values:
+* - FMI_LVD_ENABLE: Enable the LVD.
+* - FMI_LVD_DISABLE: Disable the LVD.
+* Input5 : FMI_FreqRange: specifies the working frequency range.
+* This parameter can be one of the following values:
+* - FMI_FREQ_LOW: Low working frequency (up to 66MHz).
+* - FMI_FREQ_HIGH: High working frequency (above 66MHz) .
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
+ u16 FMI_LVDEN, u16 FMI_FreqRange)
+{
+ /* Configure the write wait state value */
+ if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1)
+ {
+ FMI->CR |= FMI_WRITE_WAIT_STATE_1;
+ }
+ else
+ {
+ FMI->CR &= FMI_WRITE_WAIT_STATE_0;
+ }
+
+ /* Write a write flash configuration register command */
+ *(vu16 *)FMI_BANK_1 = 0x60;
+
+ /* Configure the flash configuration register */
+ *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03;
+}
+
+/*******************************************************************************
+* Function Name : FMI_EraseSector
+* Description : Erase the needed sector.
+* Input : FMI_Sector: specifies the sector to be erased.
+* This parameter can be one of the following values:
+* - FMI_B0S0: FMI bank 0 sector 0.
+* - FMI_B0S1: FMI bank 0 sector 1.
+* - FMI_B0S2: FMI bank 0 sector 2.
+* - FMI_B0S3: FMI bank 0 sector 3.
+* - FMI_B0S4: FMI bank 0 sector 4.
+* - FMI_B0S5: FMI bank 0 sector 5.
+* - FMI_B0S6: FMI bank 0 sector 6.
+* - FMI_B0S7: FMI bank 0 sector 7.
+* - FMI_B1S0: FMI bank 1 sector 0.
+* - FMI_B1S1: FMI bank 1 sector 1.
+* - FMI_B1S2: FMI bank 1 sector 2.
+* - FMI_B1S3: FMI bank 1 sector 3.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_EraseSector(vu32 FMI_Sector)
+{
+ /* Write an erase set-up command to the sector */
+ *(vu16 *)FMI_Sector = 0x20;
+
+ /* Write an erase confirm command to the sector */
+ *(vu16 *)FMI_Sector = 0xD0;
+}
+
+/*******************************************************************************
+* Function Name : FMI_EraseBank
+* Description : Erase the needed bank.
+* Input : FMI_Bank: specifies the bank to be erased.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_EraseBank(vu32 FMI_Bank)
+{
+ /* Write a bank erase set-up command to the bank */
+ *(vu16 *)FMI_Bank = 0x80;
+
+ /* Write an erase confirm command to the sector */
+ *(vu16 *)FMI_Bank = 0xD0;
+}
+
+/*******************************************************************************
+* Function Name : FMI_WriteHalfWord
+* Description : Write a halfword to the needed Flash memory address.
+* Input 1 : FMI_Address: specifies the address offset where the data will
+* be written.
+* Input 2 : FMI_Data: the needed data.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data)
+{
+ /* Write a program command to the sector to be written */
+ *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40;
+
+ /* Write the halfword to the destination address */
+ *(vu16 *)FMI_Address = FMI_Data;
+}
+
+/*******************************************************************************
+* Function Name : FMI_WriteOTPHalfWord
+* Description : Write a halfword to the needed OTP sector address.
+* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset
+* where the data will be written.
+* This parameter can be one of the following values:
+* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0.
+* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0.
+* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1.
+* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1.
+* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2.
+* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2.
+* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3.
+* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3.
+* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4.
+* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4.
+* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5.
+* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5.
+* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6.
+* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6.
+* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7.
+* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7.
+* Input 2 : FMI_OTPData: The needed OTP data.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData)
+{
+ /* Write a write OTP command to the needed address */
+ *(vu16 *)(FMI_BANK_1) = 0xC0;
+
+ /* Write the halfword to the destination address */
+ *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData;
+}
+
+/*******************************************************************************
+* Function Name : FMI_ReadWord
+* Description : Read the correspondent data.
+* Input : FMI_Address: specifies the needed address.
+* Output : None
+* Return : The data contained in the specified address.
+*******************************************************************************/
+u32 FMI_ReadWord(u32 FMI_Address)
+{
+ return(*(u32*)FMI_Address);
+}
+
+/*******************************************************************************
+* Function Name : FMI_ReadOTPData
+* Description : Read data from the OTP sector.
+* Input : FMI_OTPAddress: specifies the address of the data to be read.
+* This parameter can be one of the following values:
+* - FMI_OTP_WORD_0: FMI bank 0 sector 0.
+* - FMI_OTP_WORD_1: FMI bank 0 sector 1.
+* - FMI_OTP_WORD_2: FMI bank 0 sector 2.
+* - FMI_OTP_WORD_3: FMI bank 0 sector 3.
+* - FMI_OTP_WORD_4: FMI bank 0 sector 4.
+* - FMI_OTP_WORD_5: FMI bank 0 sector 5.
+* - FMI_OTP_WORD_6: FMI bank 0 sector 6.
+* - FMI_OTP_WORD_7: FMI bank 0 sector 7.
+* Output : None
+* Return : The needed OTP words.
+*******************************************************************************/
+u32 FMI_ReadOTPData(u8 FMI_OTPAddress)
+{
+ u32 OTP_Data = 0x0;
+ /* write a read OTP sector command */
+ *(vu16 *)(FMI_BANK_1) = 0x98;
+
+ /* Read the correspondent data */
+ OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress));
+
+ /* Write a read array command */
+ *(vu16 *)(FMI_BANK_1) = 0xFF;
+
+ return OTP_Data;
+}
+
+/*******************************************************************************
+* Function Name : FMI_GetFlagStatus
+* Description : Check whether the specified FMI flag is set or not.
+* Input1 : FMI_Flag: flag to check.
+* This parameter can be one of the following values:
+* - FMI_FLAG_SPS: Sector Protection Status Flag.
+* - FMI_FLAG_PSS: Program Suspend Status Flag.
+* - FMI_FLAG_PS: Program Status Flag.
+* - FMI_FLAG_ES: Erase Status Flag.
+* - FMI_FLAG_ESS: Erase Suspend Status Flag.
+* - FMI_FLAG_PECS: FPEC Status Flag.
+* Input2 : FMI_Bank: specifies the needed bank.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : None
+*******************************************************************************/
+FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank)
+{
+ u16 FMI_Status_Register = 0;
+
+ /* Write a read status register command */
+ *(vu16 *)FMI_Bank = 0x70;
+
+ /* Wait until operation completion */
+ while(!((*(vu16 *)FMI_Bank) & 0x80));
+
+ /* Read the status register */
+ FMI_Status_Register = *(vu16 *)FMI_Bank;
+
+ /* Write a read array command */
+ *(vu16 *)FMI_Bank = 0xFF;
+
+ if((FMI_Status_Register & FMI_Flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/*******************************************************************************
+* Function Name : FMI_GetReadWaitStateValue
+* Description : Get the current Read wait state value.
+* Input : None
+* Output : None
+* Return : The current read wait states value.
+*******************************************************************************/
+u16 FMI_GetReadWaitStateValue(void)
+{
+ u16 FMI_Configuration_Register = 0;
+ /* Write a read flash configuration register command */
+ *(vu16 *)FMI_BANK_1 = 0x90;
+
+ /* Read the flash configuration register */
+ FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14);
+
+ /* Write a read array command */
+ *(vu16 *)FMI_BANK_1 = 0xFF;
+
+ FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3;
+
+ /* Return the wait states value */
+ return FMI_Configuration_Register;
+}
+
+/*******************************************************************************
+* Function Name : FMI_GetWriteWaitStateValue
+* Description : Get the current write wait state value.
+* Input : None
+* Output : None
+* Return : The current write wait states value.
+*******************************************************************************/
+u16 FMI_GetWriteWaitStateValue(void)
+{
+ return ((u16)((FMI->CR & 0x100) >> 8));
+}
+
+/*******************************************************************************
+* Function Name : FMI_SuspendEnable
+* Description : Suspend command enable.
+* Input : FMI_Bank: specifies the bank to be suspended.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_SuspendEnable(vu32 FMI_Bank)
+{
+ /* Write a suspend command to the bank */
+ *(vu16 *)FMI_Bank = 0xB0;
+}
+
+/*******************************************************************************
+* Function Name : FMI_ResumeEnable
+* Description : Resume the suspended command.
+* Input : FMI_Bank: specifies the suspended bank.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_ResumeEnable(vu32 FMI_Bank)
+{
+ /* Write a resume command to the bank */
+ *(vu16 *)FMI_Bank = 0xD0;
+}
+
+/*******************************************************************************
+* Function Name : FMI_ClearFlag
+* Description : Clear the FMI Flags on the correspondent bank.
+* Input : FMI_Bank: specifies the needed bank.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_ClearFlag(vu32 FMI_Bank)
+{
+ /* Write a clear status register command */
+ *(vu16 *)FMI_Bank = 0x50;
+}
+
+/*******************************************************************************
+* Function Name : FMI_WriteProtectionCmd
+* Description : Enable or disable the write protection for the needed sector.
+* Input1 : FMI_Sector: specifies the sector to be protected or
+* unprotected.
+* This parameter can be one of the following values:
+* - FMI_B0S0: FMI bank 0 sector 0.
+* - FMI_B0S1: FMI bank 0 sector 1.
+* - FMI_B0S2: FMI bank 0 sector 2.
+* - FMI_B0S3: FMI bank 0 sector 3.
+* - FMI_B0S4: FMI bank 0 sector 4.
+* - FMI_B0S5: FMI bank 0 sector 5.
+* - FMI_B0S6: FMI bank 0 sector 6.
+* - FMI_B0S7: FMI bank 0 sector 7.
+* - FMI_B1S0: FMI bank 1 sector 0.
+* - FMI_B1S1: FMI bank 1 sector 1.
+* - FMI_B1S2: FMI bank 1 sector 2.
+* - FMI_B1S3: FMI bank 1 sector 3.
+* Input2 : FMI_NewState: specifies the protection status.
+* This parameter can be one of the following values:
+* - ENABLE: Enable the protection.
+* - DISABLE: Disable the protection.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState)
+{
+ if (FMI_NewState == ENABLE)
+ {
+ *(vu16*)FMI_Sector = 0x60;
+ *(vu16*)FMI_Sector = 0x01;
+ *(vu16*)FMI_Sector = 0xFF;
+ }
+ else /* DISABLE */
+ {
+ *(vu16*)FMI_Sector = 0x60;
+ *(vu16*)FMI_Sector = 0xD0;
+ *(vu16*)FMI_Sector = 0xFF;
+ }
+}
+
+/*******************************************************************************
+* Function Name : FMI_GetWriteProtectionStatus
+* Description : Get the write protection status for the needed sector.
+* Input : FMI_Sector_Mask: specifies the needed sector mask.
+* This parameter can be one of the following values:
+* - FMI_B0S0_MASK: FMI bank 0 sector 0.
+* - FMI_B0S1_MASK: FMI bank 0 sector 1.
+* - FMI_B0S2_MASK: FMI bank 0 sector 2.
+* - FMI_B0S3_MASK: FMI bank 0 sector 3.
+* - FMI_B0S4_MASK: FMI bank 0 sector 4.
+* - FMI_B0S5_MASK: FMI bank 0 sector 5.
+* - FMI_B0S6_MASK: FMI bank 0 sector 6.
+* - FMI_B0S7_MASK: FMI bank 0 sector 7.
+* - FMI_B1S0_MASK: FMI bank 1 sector 0.
+* - FMI_B1S1_MASK: FMI bank 1 sector 1.
+* - FMI_B1S2_MASK: FMI bank 1 sector 2.
+* - FMI_B1S3_MASK: FMI bank 1 sector 3.
+* Output : None
+* Return : The Protection Status of the needed sector.
+* - RESET: The needed sector is not write protected.
+* - SET : The needed sector is write protected.
+*******************************************************************************/
+FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask)
+{
+ u16 Protection_Level_1_Register = 0;
+ /* Write a read flash protection level 1 register command */
+ *(vu16 *)FMI_BANK_1 = 0x90;
+
+ /* Read the flash protection level 1 register */
+ Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10);
+
+ /* Write a read array command */
+ *(vu16 *)FMI_BANK_1 = 0xFF;
+
+ if (Protection_Level_1_Register &= FMI_Sector_Mask)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/*******************************************************************************
+* Function Name : FMI_WaitForLastOperation
+* Description : Wait until the last operation (Write halfword, Write OTP
+* halfword, Erase sector and Erase bank) completion.
+* Input : FMI_Bank: specifies the bank where the operation is on going.
+* This parameter can be one of the following values:
+* - FMI_BANK_0: FMI bank 0.
+* - FMI_BANK_1: FMI bank 1.
+* Output : None
+* Return : The timeout status.
+* This parameter can be one of the following values:
+* - FMI_TIME_OUT_ERROR: Timeout error occurred.
+* - FMI_NO_TIME_OUT_ERROR: No timeout error.
+*******************************************************************************/
+u8 FMI_WaitForLastOperation(vu32 FMI_Bank)
+{
+ u32 Time_Out = 0;
+
+ /* Write a read status register command */
+ *(vu16 *)(FMI_Bank) = 0x70;
+
+ /* Wait until operation compeletion */
+ while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT ))
+ {
+ Time_Out ++; /* Time Out */
+ }
+
+ /* Write a read array command */
+ *(vu16 *)FMI_Bank = 0xFF;
+
+ if (Time_Out == TIMEOUT)
+ {
+ return FMI_TIME_OUT_ERROR;
+ }
+ else
+ {
+ return FMI_NO_TIME_OUT_ERROR;
+ }
+}
+
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c b/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_gpio.c
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides all the GPIO software functions.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_gpio.h"
+#include "91x_scu.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+ static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx);
+
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : GPIO_DeInit
+* Description : Deinitializes the GPIOx peripheral registers to their default
+* reset values.
+* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+
+ /* Reset the GPIO registers values */
+ if(GPIOx == GPIO0)
+ {
+ SCU_APBPeriphReset(__GPIO0,ENABLE);
+ SCU_APBPeriphReset(__GPIO0,DISABLE);
+ SCU->GPIOTYPE[0x00] = 0x0000 ;
+ SCU->GPIOOUT[0x00] = 0x0000;
+ SCU->GPIOIN[0x00] = 0x0000;
+ }
+
+ if(GPIOx == GPIO1)
+ {
+ SCU_APBPeriphReset(__GPIO1,ENABLE);
+ SCU_APBPeriphReset(__GPIO1,DISABLE);
+ SCU->GPIOTYPE[0x01] = 0x0000 ;
+ SCU->GPIOOUT[0x01] = 0x0000;
+ SCU->GPIOIN[0x01] = 0x0000;
+ }
+
+ if(GPIOx == GPIO2)
+ {
+ SCU_APBPeriphReset(__GPIO2,ENABLE);
+ SCU_APBPeriphReset(__GPIO2,DISABLE);
+ SCU->GPIOTYPE[0x02] = 0x0000 ;
+ SCU->GPIOOUT[0x02] = 0x0000;
+ SCU->GPIOIN[0x02] = 0x0000;
+ }
+
+ if(GPIOx == GPIO3)
+ {
+ SCU_APBPeriphReset(__GPIO3,ENABLE);
+ SCU_APBPeriphReset(__GPIO3,DISABLE);
+ SCU->GPIOTYPE[0x03] = 0x0000 ;
+ SCU->GPIOOUT[0x03] = 0x0000;
+ SCU->GPIOIN[0x03] = 0x0000;
+ }
+
+ if(GPIOx == GPIO4)
+ {
+ SCU_APBPeriphReset(__GPIO4,ENABLE);
+ SCU_APBPeriphReset(__GPIO4,DISABLE);
+ SCU->GPIOTYPE[0x04] = 0x0000 ;
+ SCU->GPIOOUT[0x04] = 0x0000;
+ SCU->GPIOIN[0x04] = 0x0000;
+ SCU->GPIOANA = 0x00;
+ }
+
+ if(GPIOx == GPIO5)
+ {
+ SCU_APBPeriphReset(__GPIO5,ENABLE);
+ SCU_APBPeriphReset(__GPIO5,DISABLE);
+ SCU->GPIOTYPE[0x05] = 0x0000 ;
+ SCU->GPIOOUT[0x05] = 0x0000;
+ SCU->GPIOIN[0x05] = 0x0000;
+ }
+
+ if(GPIOx == GPIO6)
+ {
+ SCU_APBPeriphReset(__GPIO6,ENABLE);
+ SCU_APBPeriphReset(__GPIO6,DISABLE);
+ SCU->GPIOTYPE[0x06] = 0x0000 ;
+ SCU->GPIOOUT[0x06] = 0x0000;
+ SCU->GPIOIN[0x06] = 0x0000;
+ }
+
+ if(GPIOx == GPIO7)
+ {
+ SCU_APBPeriphReset(__GPIO7,ENABLE);
+ SCU_APBPeriphReset(__GPIO7,DISABLE);
+ SCU->GPIOOUT[0x07] = 0xAAAA;
+ SCU->GPIOOUT[0x07] = 0x0000;
+ SCU->GPIOIN[0x07] = 0x0000;
+ }
+
+ if(GPIOx == GPIO8)
+ {
+ SCU_APBPeriphReset(__GPIO8,ENABLE);
+ SCU_APBPeriphReset(__GPIO8,DISABLE);
+ SCU->GPIOEMI = 0x00;
+ }
+
+ if(GPIOx == GPIO9)
+ {
+ SCU_APBPeriphReset(__GPIO9,ENABLE);
+ SCU_APBPeriphReset(__GPIO9,DISABLE);
+ SCU->GPIOEMI = 0x00;
+ }
+}
+/*******************************************************************************
+* Function Name : GPIO_Init
+* Description : Initializes the GPIOx peripheral according to the specified
+* parameters in the GPIO_InitStruct .
+* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+* contains the configuration information for the specified GPIO
+* peripheral.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Select pin direction */
+ u8 PinNumber = 0;
+ u8 Counter = 0;
+ u8 GPIO_Number = 0;
+
+ GPIO_Number = GPIO_GetGPIONumber(GPIOx);
+
+
+ if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput)
+ {
+ GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin;
+ }
+
+ for (Counter = 0; Counter < 8;Counter++)
+ {
+ /*Search pin number*/
+ PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <<Counter));
+ if((PinNumber >> Counter) == 1)
+ {
+ /*Output ALternate 0*/
+ SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2));
+ if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1)
+ {
+ /*Output ALternate 1*/
+ SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2);
+ }
+ if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2)
+ {
+ /*Output ALternate 2*/
+ SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2);
+ }
+ if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3)
+ {
+ /*Output ALternate 3*/
+ SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2);
+ }
+
+ /*Type configuration: PushPull or Open Collector*/
+ SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ;
+ if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector)
+ {
+ /*Open Drain configuration*/
+ SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter;
+ }
+
+ /*IP Connected disable*/
+ SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ;
+ if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable)
+ {
+ /*IP Connected enable*/
+ SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter;
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_StructInit
+* Description : Initialize the GPIO Init Structure parameters
+* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
+* which will be initialized.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Direction = GPIO_PinInput;
+ GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull;
+ GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable;
+ GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ReadBit
+* Description : Reads the specified port pin
+* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
+* where x can be (0..7).
+* Output : None
+* Return : The port pin value
+*******************************************************************************/
+u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin)
+{
+ if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET )
+ {
+ return Bit_SET;
+ }
+ else
+ {
+ return Bit_RESET;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_Read
+* Description : Reads the specified GPIO data port
+* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* Output : None
+* Return : GPIO data port word value.
+*******************************************************************************/
+u8 GPIO_Read(GPIO_TypeDef* GPIOx)
+{
+ return (GPIOx->DR[0x3FC]);
+}
+
+/*******************************************************************************
+* Function Name : GPIO_WriteBit
+* Description : Sets or clears the selected data port bit.
+* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
+* where x can be (0..7).
+* - BitVal: this parameter specifies the value to be written
+* to the selected bit.
+* BitVal must be one of the BitAction enum values:
+* - Bit_RESET: to clear the port pin
+* - Bit_SET: to set the port pin
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal)
+{
+ if(BitVal == Bit_SET)
+ {
+ GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->DR[GPIO_Pin <<2] = 0x00;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_Write
+* Description : Writes the passed value in the selected data GPIOx port
+* register.
+* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* - PortVal: the value to be written to the data port register.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal)
+{
+ GPIOx->DR[0x3FC] = PortVal;
+}
+
+/*******************************************************************************
+* Function Name : GPIO_EMIConfig
+* Description : Enables or disables GPIO 8 and 9 in EMI mode.
+* Input : - NewState: new state of the EMI.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_EMIConfig(FunctionalState NewState)
+{
+ if(NewState == ENABLE)
+ {
+ SCU->GPIOEMI = 0x01;
+ }
+ else
+ {
+ SCU->GPIOEMI = 0x00;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_ANAPinConfig
+* Description : Enables or disables pins from GPIO 4 in Analogue mode.
+* Input :- GPIO_ANAChannel: selects the ADC channel pin.
+* This parameter can be one of the following values:
+* GPIO_ANAChannel0
+* GPIO_ANAChannel1
+* GPIO_ANAChannel2
+* GPIO_ANAChannel3
+* GPIO_ANAChannel4
+* GPIO_ANAChannel5
+* GPIO_ANAChannel6
+* GPIO_ANAChannel7
+* GPIO_ANAChannelALL
+* - NewState: new state of the port pin.
+* This parameter can be: ENABLE or DISABLE.
+* Output : None
+* Return : None
+*******************************************************************************/
+void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState)
+{
+
+ if(NewState == ENABLE)
+ {
+ if(GPIO_ANAChannel == GPIO_ANAChannelALL)
+ {
+ SCU->GPIOOUT[4] = 0x0000;
+ SCU->GPIOIN[4] = 0x00;
+ }
+ else
+ {
+ SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1));
+ SCU->GPIOIN[4] &= ~GPIO_ANAChannel;
+ }
+ SCU->GPIOANA |= GPIO_ANAChannel;
+
+ }
+ else
+ {
+ SCU->GPIOANA &= ~GPIO_ANAChannel;
+ }
+}
+
+/*******************************************************************************
+* Function Name : GPIO_GetGPIONumber
+* Description : searche the GPIO number.
+* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
+* Output : None
+* Return : GPIO number
+*******************************************************************************/
+u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx)
+{
+
+ if(GPIOx == GPIO1)
+ {
+ return 1;
+ }
+ if(GPIOx == GPIO2)
+ {
+ return 2;
+ }
+ if(GPIOx == GPIO3)
+ {
+ return 3;
+ }
+ if(GPIOx == GPIO4)
+ {
+ return 4;
+ }
+ if(GPIOx == GPIO5)
+ {
+ return 5;
+ }
+ if(GPIOx == GPIO6)
+ {
+ return 6;
+ }
+ if(GPIOx == GPIO7)
+ {
+ return 7;
+ }
+ if(GPIOx == GPIO8)
+ {
+ return 8;
+ }
+ if(GPIOx == GPIO9)
+ {
+ return 9;
+ }
+ return 0;
+}
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c b/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c new file mode 100644 index 0000000..c0eadbb --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_lib.c
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides all peripherals pointers
+ : initialization.
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+#define EXT
+
+/* Standard include ----------------------------------------------------------*/
+#include "91x_map.h"
+
+/* Include of other module interface headers ---------------------------------*/
+/* Local includes ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Interface functions -------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#ifdef DEBUG
+
+/*******************************************************************************
+* Function Name : debug
+* Description : this function initialize peripherals pointers
+* Input : no one
+* Output : no one
+* Return : no one
+*******************************************************************************/
+void debug(void)
+{
+
+
+/************************* DMA *************************/
+
+#ifdef _DMA
+ DMA = (DMA_TypeDef *)DMA_BASE;
+#endif /* _DMA */
+
+/************************* DMA *************************/
+
+
+#ifdef _DMA_Channel0
+ DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE;
+#endif /* _DMA_Channel0 */
+
+#ifdef _DMA_Channel1
+ DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE;
+#endif /* _DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE;
+#endif /* _DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE;
+#endif /* _DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE;
+#endif /* _DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE;
+#endif /* _DMA_Channel5*/
+
+
+#ifdef _DMA_Channel6
+ DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE;
+#endif /* _DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE;
+#endif /* _DMA_Channel7 */
+
+
+
+ /************************* EMI *************************/
+
+#ifdef _EMI_Bank0
+ EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE;
+#endif /* _EMI_Bank0 */
+
+#ifdef _EMI_Bank1
+ EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE;
+#endif /* _EMI_Bank1 */
+
+#ifdef _EMI_Bank2
+ EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE;
+#endif /* _EMI_Bank2 */
+
+#ifdef _EMI_Bank3
+ EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE;
+ #endif /* _EMI_Bank3 */
+
+
+
+/************************* AHBAPB *************************/
+
+#ifdef _AHBAPB0
+ AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE;
+#endif /* _AHBAPB0 */
+
+#ifdef _AHBAPB1
+ AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE;
+#endif /*_AHBAPB1 */
+
+
+
+/************************* FMI *************************/
+
+#ifdef _FMI
+ FMI = (FMI_TypeDef *)FMI_BASE;
+#endif /* _FMI */
+
+/************************* VIC *************************/
+
+#ifdef _VIC0
+ VIC0 = (VIC_TypeDef *)VIC0_BASE;
+#endif /* _VIC0 */
+
+#ifdef _VIC1
+ VIC1 = (VIC_TypeDef *)VIC1_BASE;
+#endif /* _VIC1 */
+
+/************************* WIU *************************/
+
+#ifdef _WIU
+ WIU = (WIU_TypeDef *)WIU_BASE;
+#endif /* _WIU */
+
+/************************* TIM *************************/
+
+#ifdef _TIM0
+ TIM0 = (TIM_TypeDef *)TIM0_BASE;
+#endif /* _TIM0 */
+
+#ifdef _TIM1
+ TIM1 = (TIM_TypeDef *)TIM1_BASE;
+#endif /* _TIM1 */
+
+#ifdef _TIM2
+ TIM2 = (TIM_TypeDef *)TIM2_BASE;
+#endif /* _TIM2 */
+
+#ifdef _TIM3
+ TIM3 = (TIM_TypeDef *)TIM3_BASE;
+#endif /* _TIM3 */
+
+/************************* GPIO ************************/
+
+#ifdef _GPIO0
+ GPIO0 = (GPIO_TypeDef *)GPIO0_BASE;
+#endif /* _GPIO0 */
+
+#ifdef _GPIO1
+ GPIO1 = (GPIO_TypeDef *)GPIO1_BASE;
+#endif /* _GPIO1 */
+
+#ifdef _GPIO2
+ GPIO2 = (GPIO_TypeDef *)GPIO2_BASE;
+#endif /* _GPIO2 */
+
+#ifdef _GPIO3
+ GPIO3 = (GPIO_TypeDef *)GPIO3_BASE;
+#endif /* _GPIO3 */
+
+#ifdef _GPIO4
+ GPIO4 = (GPIO_TypeDef *)GPIO4_BASE;
+#endif /* _GPIO4 */
+
+#ifdef _GPIO5
+ GPIO5 = (GPIO_TypeDef *)GPIO5_BASE;
+#endif /* _GPIO5 */
+
+#ifdef _GPIO6
+ GPIO6 = (GPIO_TypeDef *)GPIO6_BASE;
+#endif /* _GPIO6 */
+
+#ifdef _GPIO7
+ GPIO7 = (GPIO_TypeDef *)GPIO7_BASE;
+#endif /* _GPIO7 */
+
+#ifdef _GPIO8
+ GPIO8 = (GPIO_TypeDef *)GPIO8_BASE;
+#endif /* _GPIO8 */
+
+#ifdef _GPIO9
+ GPIO9 = (GPIO_TypeDef *)GPIO9_BASE;
+#endif /* _GPIO9 */
+
+/************************* RTC *************************/
+
+#ifdef _RTC
+ RTC = (RTC_TypeDef *)RTC_BASE;
+#endif /* _RTC */
+
+/************************* PRCCU ***********************/
+
+#ifdef _SCU
+ SCU = (SCU_TypeDef *)SCU_BASE;
+#endif /* _PRCCU */
+
+/************************** MC *************************/
+
+#ifdef _MC
+ MC = (MC_TypeDef *)MC_BASE;
+#endif /* _MC */
+
+/************************* UART ************************/
+
+#ifdef _UART0
+ UART0 = (UART_TypeDef *)UART0_BASE;
+#endif /* _UART0 */
+
+#ifdef _UART1
+ UART1 = (UART_TypeDef *)UART1_BASE;
+#endif /* _UART1 */
+
+#ifdef _UART2
+ UART2 = (UART_TypeDef *)UART2_BASE;
+#endif /* _UART2 */
+
+/************************* SSP *************************/
+
+#ifdef _SSP0
+ SSP0 = (SSP_TypeDef *)SSP0_BASE;
+#endif /* _SSP0 */
+
+#ifdef _SSP1
+ SSP1 = (SSP_TypeDef *)SSP1_BASE;
+#endif /* _SSP1 */
+
+/************************* CAN *************************/
+
+#ifdef _CAN
+ CAN = (CAN_TypeDef *)CAN_BASE;
+#endif /* _CAN */
+
+/************************* ADC *************************/
+
+#ifdef _ADC
+ ADC = (ADC_TypeDef *)ADC_BASE;
+#endif /* _ADC */
+
+/************************* WDG *************************/
+
+#ifdef _WDG
+ WDG = (WDG_TypeDef *)WDG_BASE;
+#endif /* _WDG */
+
+/************************* I2C *************************/
+
+#ifdef _I2C0
+ I2C0 = (I2C_TypeDef *)I2C0_BASE;
+#endif /* _I2C0 */
+
+#ifdef _I2C1
+ I2C1 = (I2C_TypeDef *)I2C1_BASE;
+#endif /* _I2C1 */
+/********************** ENET **************************/
+#ifdef _ENET
+ ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE;
+ ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE;
+#endif /* _ENET */
+}
+#endif /* DEBUG */
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c b/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
+* File Name : 91x_scu.c
+* Author : MCD Application Team
+* Date First Issued : 05/18/2006 : Version 1.0
+* Description : This file provides the SCU library software functions
+********************************************************************************
+* History:
+* 05/24/2006 : Version 1.1
+* 05/18/2006 : Version 1.0
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
+* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
+* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
+* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "91x_scu.h"
+
+/* Include of other module interface headers ---------------------------------*/
+/* Local includes ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SCU_PLLEN 0x80000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Interface functions -------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : SCU_MCLKSourceConfig
+* Description : Configures the MCLK source clock
+* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC
+* Output : None
+* Return : ErrorStatus: SUCCESS or ERROR
+* Note : this function returns ERROR if trying to select the PLL as
+* clock source while the PLL is disabled or not locked.
+*******************************************************************************/
+ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source)
+{
+ u32 CLKCNTR_Value;
+
+ CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/
+ CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/
+ if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/
+ {
+ /*check if PLL enabled & locked*/
+ if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
+ return ERROR;
+ }
+ else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/
+ SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/
+ return SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name : SCU_PLLFactorsConfig
+* Description : Sets the PLL factors
+* Input : PLLN, PLLM and PLLP
+* Output : None
+* Return : ErrorStatus: ERROR or SUCCESS
+* Notes : -The PLL factors must respect the PLL specification requirements
+* -The function returns ERROR if trying to change PLL
+* factors while PLL is selected as Main Clock source (MCLK)
+* -This function disables the PLL, to enable the PLL use
+* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors
+******************************************************************************/
+ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP)
+{
+ if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/
+ {
+ SCU->PLLCONF =0; /*clear PLLCONF register*/
+ SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/
+ SCU->PLLCONF |=PLLM; /*update PLLM field*/
+ SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/
+ return SUCCESS;
+ }
+ return ERROR;
+}
+
+/*******************************************************************************
+* Function Name : SCU_PLLCmd
+* Description : Enable or Disable the PLL
+* Input : NewState = ENABLE or DISABLE
+* Output : None
+* Return : ErrorStatus: SUCCESS or ERROR
+* Note : -The function returns ERROR if:
+* *trying to disable the PLL while it is selected as the MCLK
+* *trying to enable the PLL while it is already enabled and
+* locked
+*******************************************************************************/
+ErrorStatus SCU_PLLCmd(FunctionalState NewState)
+{
+ vu32 i;
+ if (NewState==ENABLE)
+ {
+ if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
+ {
+ SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/
+ SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/
+ while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/
+ return SUCCESS;
+ }
+ else return ERROR;
+ }
+ else /*NewState = DISABLE*/
+ {
+ if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/
+ {
+ for(i=10;i>0;i--); /*delay before PLL disabling*/
+ SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/
+ return SUCCESS;
+ }
+ else return ERROR;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SCU_RCLKDivisorConfig
+* Description : Sets the RCLK divisor value
+* Input : RCLK_Divisor
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_RCLKDivisorConfig(u32 RCLK_Divisor)
+{
+ SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/
+ if (RCLK_Divisor!=SCU_RCLK_Div1)
+ SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_HCLKDivisorConfig
+* Description : Sets the HCLK divisor value
+* Input : HCLK_Divisor
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_HCLKDivisorConfig(u32 HCLK_Divisor)
+{
+ SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/
+ if (HCLK_Divisor!=SCU_HCLK_Div1)
+ SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_PCLKDivisorConfig
+* Description : Sets the PCLK divisor value
+* Input : PCLK_Divisor
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_PCLKDivisorConfig(u32 PCLK_Divisor)
+{
+ SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/
+ if (PCLK_Divisor!=SCU_PCLK_Div1)
+ SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_APBPeriphClockConfig
+* Description : Enable the clock for an APB peripheral
+* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...)
+* -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE) /*Enable clock for APB peripheral*/
+ SCU->PCGR1 |=APBPeriph;
+ else
+ SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_AHBPeriphClockConfig
+* Description : Enable the clock for an AHB peripheral
+* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...)
+* -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE) /*Enable clock for AHB peripheral*/
+ SCU->PCGRO |=AHBPeriph;
+ else
+ SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_APBPeriphReset
+* Description : Assert or deassert Reset on APB peripheral
+* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState)
+{
+ if (NewState==DISABLE) /*APB peripheral not held in Reset*/
+ SCU->PRR1 |=APBPeriph;
+ else
+ SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_AHBPeriphReset
+* Description : Assert or deassert Reset on AHB peripheral
+* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState)
+{
+ if (NewState==DISABLE)
+ SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/
+ else
+ SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_APBPeriphIdleConfig
+* Description : Enable or Disable Periph Clock during Idle mode
+* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/
+ else
+ SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_AHBPeriphIdleConfig
+* Description : Enable or Disable Periph Clock during Idle mode
+* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/
+ else
+ SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_APBPeriphDebugConfig
+* Description : Enable or Disable Periph Clock during ARM debug state
+* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/
+ else
+ SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_AHBPeriphDebugConfig
+* Description : Enable or Disable Periph Clock during ARM debug state
+* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
+ -NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/
+ else
+ SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/
+}
+/*******************************************************************************
+* Function Name : SCU_BRCLKDivisorConfig
+* Description : Sets the BRCLK divisor value
+* Input : BRCLK_Divisor
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor)
+{
+ SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/
+ if (BRCLK_Divisor!=SCU_BRCLK_Div1)
+ SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_TIMCLKSourceConfig
+* Description : Sets the TIMx clock source
+* Input : - TIMx : SCU_TIM01 or SCU_TIM23
+* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source)
+{
+ if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/
+ {
+ SCU->CLKCNTR &=0xFFFFDFFF;
+ if (TIMCLK_Source == SCU_TIMCLK_EXT)
+ SCU->CLKCNTR |=0x2000;
+ }
+ else
+ {
+ SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/
+ if (TIMCLK_Source == SCU_TIMCLK_EXT)
+ SCU->CLKCNTR |=0x4000;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SCU_TIMPresConfig
+* Description : Sets the TIMx Prescaler Value
+* Input : - TIMx : SCU_TIM01 or SCU_TIM23
+* - Prescaler (16 bit value)
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler)
+{
+ if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/
+ SCU->SCR1 = Prescaler&0xFFFF;
+ else
+ SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_USBCLKConfig
+* Description : Configures the clock source for the 48MHz USBCLK
+* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_USBCLKConfig(u32 USBCLK_Source)
+{
+ SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/
+ if (USBCLK_Source!=SCU_USBCLK_MCLK)
+ SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_PHYCLKConfig
+* Description : Enable or Disable PHY clock output
+* Input : NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_PHYCLKConfig(FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/
+ else
+ SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_FMICLKDivisorConfig
+* Description : Set the FMI clock divisor
+* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor)
+{
+ SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/
+ if (FMICLK_Divisor!=SCU_FMICLK_Div1)
+ SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */
+}
+
+/*******************************************************************************
+* Function Name : SCU_EMIBCLKDivisorConfig
+* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2
+* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK)
+{
+ SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */
+ if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1)
+ SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */
+}
+
+/*******************************************************************************
+* Function Name : SCU_EMIModeConfig
+* Description : Configure the EMI as Multiplexed or Demultiplexed
+* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_EMIModeConfig(u32 SCU_EMIMODE)
+{
+ SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/
+ if (SCU_EMIMODE!=SCU_EMI_MUX)
+ SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_EMIALEConfig
+* Description : Configure the ALE signal (length & polarity)
+* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2
+* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL)
+{
+ /*Configure EMI ALE Length*/
+ SCU->SCR0 &=SCU_EMIALE_LEN1;
+ if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1)
+ SCU->SCR0 |= SCU_EMIALE_LEN2;
+
+ /*Configure EMI ALE POL*/
+ SCU->SCR0 &=SCU_EMIALE_POLLow;
+ if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow)
+ SCU->SCR0 |= SCU_EMIALE_POLHigh;
+}
+
+/*******************************************************************************
+* Function Name : SCU_ITConfig
+* Description : ENBALE or DISABLE an SCU interrupt
+* Input : -SCU_IT: interrupt mask
+* -NewState: ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->ITCMSK&=~SCU_IT; /*IT enable */
+ else
+ SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/
+}
+
+/*******************************************************************************
+* Function Name : SCU_GetFlagStatus
+* Description : Returns flag status
+* Input : SCU_Flag
+* Output : NONE
+* Return : SET or RESET
+*******************************************************************************/
+FlagStatus SCU_GetFlagStatus(u32 SCU_Flag)
+{
+ if (SCU->SYSSTATUS&SCU_Flag)
+ return SET;
+ else return RESET;
+}
+
+/*******************************************************************************
+* Function Name : SCU_ClearFlag
+* Description : Clears a SYSTATUS Flag
+* Input : SCU_Flag
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_ClearFlag(u32 SCU_Flag)
+{
+ SCU->SYSSTATUS = SCU_Flag;
+}
+/*******************************************************************************
+* Function Name : SCU_GetPLLfreqValue
+* Description : Gets the current PLL frequency
+* Input : None
+* Output : None
+* Return : PLL frequency (KHz)
+*******************************************************************************/
+u32 SCU_GetPLLFreqValue(void)
+{
+ u8 PLL_M;
+ u8 PLL_N;
+ u8 PLL_P;
+
+ PLL_M = SCU->PLLCONF&0xFF;
+ PLL_N = (SCU->PLLCONF&0xFF00)>>8;
+ PLL_P = (SCU->PLLCONF&0x70000)>>16;
+
+ if ((PLL_M>0)&&(PLL_N>0))
+ return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<<PLL_P));
+
+ else return 0;
+}
+/*******************************************************************************
+* Function Name : SCU_GetMCLKFreqValue
+* Description : Gets the current MCLK frequency
+* Input : None
+* Output : None
+* Return : MCLK frequency (KHz)
+*******************************************************************************/
+u32 SCU_GetMCLKFreqValue(void)
+{
+ if ((SCU->CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal);
+ if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32);
+ else return (SCU_GetPLLFreqValue());
+}
+
+/*******************************************************************************
+* Function Name : SCU_GetRCLKFreqValue
+* Description : Gets the current RCLK frequency
+* Input : None
+* Output : None
+* Return : RCLK frequency (KHz)
+*******************************************************************************/
+u32 SCU_GetRCLKFreqValue(void)
+{
+ u8 RCLK_Div;
+ RCLK_Div = (SCU->CLKCNTR&0x1C)>>2;
+ if (RCLK_Div==0x5) RCLK_Div=10;
+ return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div);
+}
+
+/*******************************************************************************
+* Function Name : SCU_GetHCLKFreqValue
+* Description : Gets the current PCLK frequency
+* Input : None
+* Output : None
+* Return : HCLK frequency (KHz)
+*******************************************************************************/
+u32 SCU_GetHCLKFreqValue(void)
+{
+ u8 HCLK_Div;
+ HCLK_Div = (SCU->CLKCNTR&0x60)>>5;
+ return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div);
+}
+
+/*******************************************************************************
+* Function Name : SCU_GetPCLKFreqValue
+* Description : Gets the current HCLK frequency
+* Input : None
+* Output : None
+* Return : PCLK frequency (KHz)
+*******************************************************************************/
+u32 SCU_GetPCLKFreqValue(void)
+{
+ u8 PCLK_Div;
+ PCLK_Div = (SCU->CLKCNTR&0x180)>>7;
+ return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div);
+}
+
+/*******************************************************************************
+* Function Name : SCU_WakeUpLineConfig
+* Description : Configures an External interrupt as WakeUp line
+* Input : EXTint : 0 -> 31
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_WakeUpLineConfig(u8 EXTint)
+{
+ if (EXTint < 8)
+ {
+ SCU->WKUPSEL&=~0x7;
+ SCU->WKUPSEL|=EXTint;
+ }
+ else if (EXTint<16)
+ {
+ SCU->WKUPSEL&=~0x38;
+ SCU->WKUPSEL|=(EXTint-8)<<3;
+ }
+ else if (EXTint<24)
+ {
+ SCU->WKUPSEL&=~0x1C0;
+ SCU->WKUPSEL|=(EXTint-16)<<6;
+ }
+ else
+ {
+ SCU->WKUPSEL&=~0xE00;
+ SCU->WKUPSEL|=(EXTint-24)<<9;
+ }
+}
+
+/*******************************************************************************
+* Function Name : SCU_SpecIntRunModeConfig
+* Description : Enables or Disables the Special Run mode
+* Input : newstate = ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_SpecIntRunModeConfig(FunctionalState NewState)
+{
+ if (NewState == ENABLE)
+ SCU->PWRMNG |=0x8;
+ else
+ SCU->PWRMNG &=~0x8;
+}
+/*******************************************************************************
+* Function Name : SCU_EnterIdleMode
+* Description : Enters in Idle mode
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_EnterIdleMode(void)
+{
+ SCU->PWRMNG |=0x1;
+}
+/*******************************************************************************
+* Function Name : SCU_EnterSleepMode
+* Description : Enters in Sleep mode
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_EnterSleepMode(void)
+{
+ SCU->PWRMNG |=0x2;
+}
+
+/*******************************************************************************
+* Function Name : SCU_UARTIrDAConfig
+* Description : Enable or Disable the Irda mode for UARTx
+* Input : - UARTx :x=0,1 or 2
+* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode)
+{
+ if (UART_IrDA_Mode == SCU_UARTMode_IrDA)
+ {
+ if (UARTx== UART0) SCU->SCR0 |=0x400;
+ else if (UARTx==UART1) SCU->SCR0 |=0x800;
+ else SCU->SCR0 |=0x1000;
+ }
+ else
+ {
+ if (UARTx== UART0) SCU->SCR0 &=~0x400;
+ else if (UARTx==UART1) SCU->SCR0 &=~0x800;
+ else SCU->SCR0 &=~0x1000;
+ }
+}
+/*******************************************************************************
+* Function Name : SCU_PFQBCCmd
+* Description : Enable or Disable PFQBC
+* Input : NewState : ENABLE or DISABLE
+* Output : None
+* Return : None
+*******************************************************************************/
+void SCU_PFQBCCmd(FunctionalState NewState)
+{
+ if (NewState==ENABLE)
+ SCU->SCR0 |=0x1;
+ else SCU->SCR0 &=~0x1;
+}
+
+/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
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