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| author | Bert Lange <b.lange@fzd.de> | 2011-11-07 15:41:50 +0100 |
|---|---|---|
| committer | Bert Lange <b.lange@fzd.de> | 2011-11-07 15:41:50 +0100 |
| commit | d190f1c37139ec38667a3d6e566dbe1b0549f84d (patch) | |
| tree | 7885f39318cb7852afc24992dd08cb6bb953ac03 /uc_str912/prj_blinky_complex_startup/inthandler.S | |
| parent | acc2681723f43b3c8ccb29055bec9d63cb863c78 (diff) | |
| download | zpu-d190f1c37139ec38667a3d6e566dbe1b0549f84d.zip zpu-d190f1c37139ec38667a3d6e566dbe1b0549f84d.tar.gz | |
initial commit
Diffstat (limited to 'uc_str912/prj_blinky_complex_startup/inthandler.S')
| -rw-r--r-- | uc_str912/prj_blinky_complex_startup/inthandler.S | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/uc_str912/prj_blinky_complex_startup/inthandler.S b/uc_str912/prj_blinky_complex_startup/inthandler.S new file mode 100644 index 0000000..09fea2f --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/inthandler.S @@ -0,0 +1,94 @@ +# Hitex/We/26.04.2006
+# primary interrupt service
+
+# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
+
+ .equ Mode_USR, 0x10
+ .equ Mode_FIQ, 0x11
+ .equ Mode_IRQ, 0x12
+ .equ Mode_SVC, 0x13
+ .equ Mode_ABT, 0x17
+ .equ Mode_UND, 0x1B
+ .equ Mode_SYS, 0x1F
+
+ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
+ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
+
+ .text
+# generate arm instructions (.code32)
+ .arm
+ .extern UART1_isr
+ .global UART1_IRQHandler /*_uart1_srv*/
+ .global _disableInterrupts
+ .global _enableInterrupts
+
+
+# enable FIQ interrupts
+
+ .func _enableInterrupts
+_enableInterrupts:
+ stmfd sp!, {r1}
+ mrs r1, CPSR
+ bic r1, r1, #I_BIT
+ bic r1, r1, #F_BIT
+ msr CPSR_c, r1
+ ldmfd sp!, {r1}
+ mov pc, r14
+ .size __enableInterrupts, . - __enableInterrupts
+ .endfunc
+
+
+#disable FIQ interrupts
+
+ .func _disableInterrupts
+_disableInterrupts:
+ stmfd sp!, {r1}
+ mrs r1, CPSR
+ orr r1, r1, #0x40
+ msr CPSR_c, r1
+ ldmfd sp!, {r1}
+ mov pc, r14
+ .size __disableInterrupts, . - __disableInterrupts
+ .endfunc
+
+
+###################################################
+#
+# primary interrupt services
+#
+###################################################
+.macro SvCon
+# Adjust and save LR_irq in IRQ stack
+ sub r14, r14, #4
+ stmfd sp!, {r14}
+
+# Save SPSR and r0 in IRQ stack
+ mrs r14, SPSR
+ stmfd sp!, {r0, r1, r14}
+
+# Save used registers and LR in User Stack
+ stmfd sp!, { r1-r3, r12, r14}
+.endm
+.macro RsCon
+# Restore used registers and LR from User Stack
+ ldmia sp!, { r1-r3, r12, r14}
+
+# Restore SPSR_irq and r0 from IRQ stack
+ ldmia sp!, {r0, r1, r14}
+ msr SPSR_cxsf, r14
+# Restore adjusted LR_irq from IRQ stack directly in the PC
+ ldmia sp!, {pc}^
+.endm
+
+#inthandler entries
+ .func UART1_IRQHandler /*_uart1_srv*/
+UART1_IRQHandler: /*_uart1_srv:*/
+ SvCon
+# enter ISR
+ bl UART1_isr /* branch to isr */
+# back from ISR
+ RsCon
+ .size __uart1_srv, . - __uart1_srv
+ .endfunc
+
+.end
|
