add: new toplevel with siumlation

2 files changed, 27 insertions, 20 deletions

diff --git a/tools/rtl/edge_detect_synchronizer.vhd b/tools/rtl/edge_detect_synchronizer.vhd
index 5854288..b93dc16 100644
--- a/tools/rtl/edge_detect_synchronizer.vhd
+++ b/tools/rtl/edge_detect_synchronizer.vhd
@@ -16,7 +16,7 @@ use ieee.std_logic_1164.all;
 
 entity edge_detect_synchronizer is
     generic (
-        rising_edge : boolean := true
+        detect_rising_edge : boolean := true
     );
     port (
         clk    : std_ulogic;
@@ -42,7 +42,7 @@ begin
         in_stage_d2  <= in_stage_d1; -- third ff
     end process;
 
-    synced <= in_stage_d1 and not in_stage_d2 when rising_edge else
+    synced <= in_stage_d1 and not in_stage_d2 when detect_rising_edge else
               not in_stage_d1 and in_stage_d2;
 
 end architecture rtl;
diff --git a/tools/rtl/synchronizer_package.vhd b/tools/rtl/synchronizer_package.vhd
index b8753dc..4a58a3a 100644
--- a/tools/rtl/synchronizer_package.vhd
+++ b/tools/rtl/synchronizer_package.vhd
@@ -5,25 +5,32 @@
 -- $Revision: 659 $
 --------------------------------------------------------------------------------
 
+library ieee;
+use ieee. std_logic_1164.all;
+
+
 package synchronizer_package is
 
 
-entity level_synchronizer is
-    port (
-        clk    : std_ulogic;
-        input  : in std_logic;
-        synced : out std_ulogic
-    );
-end entity level_synchronizer;
-
-
-entity edge_detect_synchronizer is
-    generic (
-        rising_edge : boolean := true
-    );
-    port (
-        clk    : std_ulogic;
-        input  : in std_logic;
-        synced : out std_ulogic
-    );
+    component level_synchronizer is
+        port (
+            clk    : std_ulogic;
+            input  : in std_logic;
+            synced : out std_ulogic
+        );
+    end component level_synchronizer;
+
+
+    component edge_detect_synchronizer is
+        generic (
+            detect_rising_edge : boolean := true
+        );
+        port (
+            clk    : std_ulogic;
+            input  : in std_logic;
+            synced : out std_ulogic
+        );
+    end component edge_detect_synchronizer;
+
+
 end package synchronizer_package;