diff options
| author | Bert Lange <b.lange@fzd.de> | 2010-08-05 18:15:43 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@fzd.de> | 2010-08-05 18:15:43 +0200 |
| commit | 53bc7b8233c432f70ba0cbfe4387fb77a6cddfa9 (patch) | |
| tree | 825660b430cb6a1a4585ccfe8efb5961bc944023 /techmap | |
| parent | 2e60bbbc95483cac9f6ecba732424cf6c08a821d (diff) | |
| download | zpu-53bc7b8233c432f70ba0cbfe4387fb77a6cddfa9.zip zpu-53bc7b8233c432f70ba0cbfe4387fb77a6cddfa9.tar.gz | |
add: ethernet core
Diffstat (limited to 'techmap')
| -rw-r--r-- | techmap/Makefile | 5 | ||||
| -rw-r--r-- | techmap/rtl/allmem.vhd | 773 | ||||
| -rw-r--r-- | techmap/rtl/gencomp.vhd | 1013 | ||||
| -rw-r--r-- | techmap/rtl/memory_inferred.vhd | 279 | ||||
| -rw-r--r-- | techmap/rtl/netcomp.vhd | 816 | ||||
| -rw-r--r-- | techmap/rtl/syncram_2p.vhd | 269 | ||||
| -rw-r--r-- | techmap/sim/Makefile | 33 | ||||
| -rw-r--r-- | techmap/sim/modelsim.ini | 58 |
8 files changed, 3246 insertions, 0 deletions
diff --git a/techmap/Makefile b/techmap/Makefile new file mode 100644 index 0000000..2c571b1 --- /dev/null +++ b/techmap/Makefile @@ -0,0 +1,5 @@ +DIRS = sim + +all: + for i in $(DIRS); do make --directory $$i; done + diff --git a/techmap/rtl/allmem.vhd b/techmap/rtl/allmem.vhd new file mode 100644 index 0000000..6bb8a13 --- /dev/null +++ b/techmap/rtl/allmem.vhd @@ -0,0 +1,773 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2010, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Package: allmem +-- File: allmem.vhd +-- Author: Jiri Gaisler Gaisler Research +-- Description: All tech specific memories +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +package allmem is + +-- AX & RTAX family + + component axcel_syncram + generic ( abits : integer := 10; dbits : integer := 8); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component axcel_syncram_2p + generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer:= 0); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + +-- Proasic + Proasicplus family + + component proasic_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component proasic_syncram_2p + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + +-- Proasic3 family + + component proasic3_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component proasic3_syncram_2p + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + + component proasic3_syncram_dp is + generic ( abits : integer := 6; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + +-- Fusion family + + component fusion_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component fusion_syncram_2p + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + + component fusion_syncram_dp is + generic ( abits : integer := 6; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + +component altera_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); +end component; + +component altera_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); +end component; + +component generic_syncram + generic (abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + write : in std_ulogic + ); +end component; + +component generic_syncram_2p + generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0); + port ( + rclk : in std_ulogic; + wclk : in std_ulogic; + rdaddress: in std_logic_vector (abits -1 downto 0); + wraddress: in std_logic_vector (abits -1 downto 0); + data: in std_logic_vector (dbits -1 downto 0); + wren : in std_ulogic; + q: out std_logic_vector (dbits -1 downto 0) + ); +end component; + +component generic_syncram_reg + generic (abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + write : in std_ulogic + ); +end component; + +component generic_syncram_2p_reg + generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0); + port ( + rclk : in std_ulogic; + wclk : in std_ulogic; + rdaddress: in std_logic_vector (abits -1 downto 0); + wraddress: in std_logic_vector (abits -1 downto 0); + data: in std_logic_vector (dbits -1 downto 0); + wren : in std_ulogic; + q: out std_logic_vector (dbits -1 downto 0) + ); +end component; + +-- synchronous 3-port regfile (2 read, 1 write port) + + component generic_regfile_3p + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32; + wrfst : integer := 0; numregs : integer := 40); + port ( + wclk : in std_ulogic; + waddr : in std_logic_vector((abits -1) downto 0); + wdata : in std_logic_vector((dbits -1) downto 0); + we : in std_ulogic; + rclk : in std_ulogic; + raddr1 : in std_logic_vector((abits -1) downto 0); + re1 : in std_ulogic; + rdata1 : out std_logic_vector((dbits -1) downto 0); + raddr2 : in std_logic_vector((abits -1) downto 0); + re2 : in std_ulogic; + rdata2 : out std_logic_vector((dbits -1) downto 0) + ); + end component; + + component ihp25_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_logic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_logic; + write : in std_logic + ); + end component; + + component ec_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component ec_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + + component rh_lib18t_syncram_2p + generic (abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + diagin : in std_logic_vector(3 downto 0)); + end component; + + component rh_lib18t_syncram is + generic (abits : integer := 6; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic; + diagin : in std_logic_vector(1 downto 0) := "00"); + end component; + + component umc_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component rhumc_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component virage_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component virage_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic); + end component; + + component virage90_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component virtex_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component virtex_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + + component unisim_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component unisim_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + + component unisim_syncram64 + generic ( abits : integer := 9); + port ( + clk : in std_ulogic; + address : in std_logic_vector (abits -1 downto 0); + datain : in std_logic_vector (63 downto 0); + dataout : out std_logic_vector (63 downto 0); + enable : in std_logic_vector (1 downto 0); + write : in std_logic_vector (1 downto 0) + ); + end component; + + component virage90_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + + component ut025crh_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component ut025crh_syncram_2p + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + + component peregrine_regfile_3p + generic (abits : integer := 6; dbits : integer := 32); + port ( + wclk : in std_ulogic; + waddr : in std_logic_vector((abits -1) downto 0); + wdata : in std_logic_vector((dbits -1) downto 0); + we : in std_ulogic; + raddr1 : in std_logic_vector((abits -1) downto 0); + re1 : in std_ulogic; + rdata1 : out std_logic_vector((dbits -1) downto 0); + raddr2 : in std_logic_vector((abits -1) downto 0); + re2 : in std_ulogic; + rdata2 : out std_logic_vector((dbits -1) downto 0)); + end component; + + component eclipse_syncram_2p is + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + rena : in std_ulogic; + raddr : in std_logic_vector (abits -1 downto 0); + dout : out std_logic_vector (dbits -1 downto 0); + wclk : in std_ulogic; + waddr : in std_logic_vector (abits -1 downto 0); + din : in std_logic_vector (dbits -1 downto 0); + write : in std_ulogic); + end component; + + component nextreme_syncram_2p is + generic (abits : integer := 6; dbits : integer := 8); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component custom1_syncram_2p is + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component artisan_syncram_2p is + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component smic13_syncram_2p is + generic ( abits : integer := 8; dbits : integer := 32); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component ihp25rh_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_logic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_logic; + write : in std_logic); + end component; + + component peregrine_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component artisan_syncram + generic ( abits : integer := 10; dbits : integer := 32 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component smic13_syncram + generic ( abits : integer := 10; dbits : integer := 32 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component custom1_syncram + generic ( abits : integer := 10; dbits : integer := 32 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic + ); + end component; + + component nextreme_syncram + generic (abits : integer := 6; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic); + end component; + + component unisim_syncram_2p is + generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0; + wrfst : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component virage_syncram_2p + generic (abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0)); + end component; + + component atc18rha_syncram + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector(abits -1 downto 0); + datain : in std_logic_vector(dbits -1 downto 0); + dataout : out std_logic_vector(dbits -1 downto 0); + enable : in std_ulogic; + write : in std_ulogic; + testin : in std_logic_vector(3 downto 0)); + end component; + + component atc18rha_syncram_dp + generic ( abits : integer := 10; dbits : integer := 8); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic; + testin : in std_logic_vector(3 downto 0)); + end component; + + component atc18rha_syncram_2p + generic ( abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + testin : in std_logic_vector(3 downto 0)); + end component; + + component artisan_syncram_dp + generic ( abits : integer := 10; dbits : integer := 32 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + + component smic13_syncram_dp + generic ( abits : integer := 10; dbits : integer := 32 ); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic + ); + end component; + +end; diff --git a/techmap/rtl/gencomp.vhd b/techmap/rtl/gencomp.vhd new file mode 100644 index 0000000..10199fe --- /dev/null +++ b/techmap/rtl/gencomp.vhd @@ -0,0 +1,1013 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2010, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Package: gencomp +-- File: gencomp.vhd +-- Author: Jiri Gaisler et al. - Aeroflex Gaisler +-- Description: Declaration of portable memory modules, pads, e.t.c. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; + +package gencomp is + +--------------------------------------------------------------------------- +-- BASIC DECLARATIONS +--------------------------------------------------------------------------- + +-- technologies and libraries + +constant NTECH : integer := 37; +type tech_ability_type is array (0 to NTECH) of integer; + +constant inferred : integer := 0; +constant virtex : integer := 1; +constant virtex2 : integer := 2; +constant memvirage : integer := 3; +constant axcel : integer := 4; +constant proasic : integer := 5; +constant atc18s : integer := 6; +constant altera : integer := 7; +constant umc : integer := 8; +constant rhumc : integer := 9; +constant apa3 : integer := 10; +constant spartan3 : integer := 11; +constant ihp25 : integer := 12; +constant rhlib18t : integer := 13; +constant virtex4 : integer := 14; +constant lattice : integer := 15; +constant ut25 : integer := 16; +constant spartan3e : integer := 17; +constant peregrine : integer := 18; +constant memartisan : integer := 19; +constant virtex5 : integer := 20; +constant custom1 : integer := 21; +constant ihp25rh : integer := 22; +constant stratix1 : integer := 23; +constant stratix2 : integer := 24; +constant eclipse : integer := 25; +constant stratix3 : integer := 26; +constant cyclone3 : integer := 27; +constant memvirage90 : integer := 28; +constant tsmc90 : integer := 29; +constant easic90 : integer := 30; +constant atc18rha : integer := 31; +constant smic013 : integer := 32; +constant tm65gpl : integer := 33; +constant axdsp : integer := 34; +constant spartan6 : integer := 35; +constant virtex6 : integer := 36; +constant actfus : integer := 37; + +constant DEFMEMTECH : integer := inferred; +constant DEFPADTECH : integer := inferred; +constant DEFFABTECH : integer := inferred; + +constant is_fpga : tech_ability_type := + (inferred => 1, virtex => 1, virtex2 => 1, axcel => 1, + proasic => 1, altera => 1, apa3 => 1, spartan3 => 1, + virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1, + stratix1 => 1, stratix2 => 1, eclipse => 1, + stratix3 => 1, cyclone3 => 1, axdsp => 1, + spartan6 => 1, virtex6 => 1, actfus => 1, others => 0); + +constant infer_mul : tech_ability_type := is_fpga; + +constant syncram_2p_write_through : tech_ability_type := + (rhumc => 1, eclipse => 1, others => 0); + +constant regfile_3p_write_through : tech_ability_type := + (rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0); + +constant regfile_3p_infer : tech_ability_type := + (inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0, + peregrine => 1, ihp25rh => 1, umc => 1, others => 0); + +constant syncram_2p_dest_rw_collision : tech_ability_type := + (memartisan => 1, smic013 => 1, others => 0); + +constant syncram_dp_dest_rw_collision : tech_ability_type := + (memartisan => 1, smic013 => 1, others => 0); + +constant has_sram : tech_ability_type := + (atc18s => 0, others => 1); + +constant has_2pram : tech_ability_type := + ( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1); + +constant has_dpram : tech_ability_type := + (virtex => 1, virtex2 => 1, memvirage => 1, axcel => 1, + altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1, + lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1, + custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1, + cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1, + tm65gpl => 1, axdsp => 1, spartan6 => 1, virtex6 => 1, + actfus => 1, others => 0); + +constant has_sram64 : tech_ability_type := + (inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1, + spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1, + spartan6 => 1, virtex6 => 1, others => 0); + +constant padoen_polarity : tech_ability_type := + (axcel => 1, proasic => 1, umc => 1, rhumc => 1, apa3 => 1, + ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1, + actfus => 1, others => 0); + +constant has_pads : tech_ability_type := + (inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0, + axcel => 1, proasic => 1, atc18s => 1, altera => 0, + umc => 1, rhumc => 1, apa3 => 1, spartan3 => 1, + ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0, + ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1, + easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1, + actfus => 1, others => 0); + +constant has_ds_pads : tech_ability_type := + (inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0, + axcel => 1, proasic => 0, atc18s => 0, altera => 0, + umc => 0, rhumc => 0, apa3 => 1, spartan3 => 1, + ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0, + ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1, + spartan6 => 1, virtex6 => 1, actfus => 1, others => 0); + +constant has_ds_combo : tech_ability_type := + ( rhumc => 1, ut25 => 1, others => 0); + +constant has_clkand : tech_ability_type := + ( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1, + virtex5 => 1, ut25 => 1, rhlib18t => 1, + spartan6 => 1, virtex6 => 1, others => 0); + +constant has_clkmux : tech_ability_type := + ( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, + virtex4 => 1, virtex5 => 1, rhlib18t => 1, + spartan6 => 1, virtex6 => 1, others => 0); + +constant has_techbuf : tech_ability_type := + ( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, + spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1, + apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1, others => 0); + +constant has_tapsel : tech_ability_type := + ( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, + spartan3 => 1, spartan3e => 1, + spartan6 => 1, virtex6 => 1, others => 0); + +constant need_extra_sync_reset : tech_ability_type := + (axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, tsmc90 => 1, + rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gpl => 1, + axdsp => 1, others => 0); + +constant is_unisim : tech_ability_type := + ( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, + spartan3 => 1, spartan3e => 1, + spartan6 => 1, virtex6 => 1, others => 0); + +-- pragma translate_off + + subtype tech_description is string(1 to 10); + + type tech_table_type is array (0 to NTECH) of tech_description; +------------------------------------------------------------------------------- + constant tech_table : tech_table_type := ( + inferred => "inferred ", virtex => "virtex ", + virtex2 => "virtex2 ", memvirage => "virage ", + axcel => "axcel ", proasic => "proasic ", + atc18s => "atc18s ", altera => "altera ", + umc => "umc18 ", rhumc => "rhumc ", + apa3 => "proasic3 ", spartan3 => "spartan3 ", + ihp25 => "ihp25 ", rhlib18t => "rhlib18t ", + virtex4 => "virtex4 ", lattice => "lattice ", + ut25 => "ut025crh ", spartan3e => "spartan3e ", + peregrine => "peregrine ", memartisan => "artisan ", + virtex5 => "virtex5 ", custom1 => "custom1 ", + ihp25rh => "ihp25rh ", stratix1 => "stratix ", + stratix2 => "stratixii ", eclipse => "eclipse ", + stratix3 => "stratixiii", cyclone3 => "cycloneiii", + memvirage90 => "virage90 ", tsmc90 => "tsmc90 ", + easic90 => "nextreme ", atc18rha => "atc18rha ", + smic013 => "smic13 ", tm65gpl => "tm65gplus ", + axdsp => "axdsp ", spartan6 => "spartan6 ", + virtex6 => "virtex6 ", actfus => "fusion " +); + +-- pragma translate_on + +-- input/output voltage + +constant x18v : integer := 1; +constant x25v : integer := 2; +constant x33v : integer := 3; +constant x50v : integer := 5; + +-- input/output levels + +constant ttl : integer := 0; +constant cmos : integer := 1; +constant pci33 : integer := 2; +constant pci66 : integer := 3; +constant lvds : integer := 4; +constant sstl2_i : integer := 5; +constant sstl2_ii : integer := 6; +constant sstl3_i : integer := 7; +constant sstl3_ii : integer := 8; +constant sstl18_i : integer := 9; +constant sstl18_ii: integer := 10; +constant lvpecl : integer := 11; + +-- pad types + +constant normal : integer := 0; +constant pullup : integer := 1; +constant pulldown : integer := 2; +constant opendrain: integer := 3; +constant schmitt : integer := 4; +constant dci : integer := 5; + +--------------------------------------------------------------------------- +-- MEMORY +--------------------------------------------------------------------------- + +-- synchronous single-port ram + component syncram + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + testen : integer := 0); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + enable : in std_ulogic; + write : in std_ulogic; + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + +-- synchronous two-port ram (1 read, 1 write port) + component syncram_2p + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + +-- synchronous dual-port ram (2 read/write ports) + component syncram_dp + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + testen : integer := 0); + port ( + clk1 : in std_ulogic; + address1 : in std_logic_vector((abits -1) downto 0); + datain1 : in std_logic_vector((dbits -1) downto 0); + dataout1 : out std_logic_vector((dbits -1) downto 0); + enable1 : in std_ulogic; + write1 : in std_ulogic; + clk2 : in std_ulogic; + address2 : in std_logic_vector((abits -1) downto 0); + datain2 : in std_logic_vector((dbits -1) downto 0); + dataout2 : out std_logic_vector((dbits -1) downto 0); + enable2 : in std_ulogic; + write2 : in std_ulogic; + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + +-- synchronous 3-port regfile (2 read, 1 write port) + component regfile_3p + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + wrfst : integer := 0; numregs : integer := 64; testen : integer := 0); + port ( + wclk : in std_ulogic; + waddr : in std_logic_vector((abits -1) downto 0); + wdata : in std_logic_vector((dbits -1) downto 0); + we : in std_ulogic; + rclk : in std_ulogic; + raddr1 : in std_logic_vector((abits -1) downto 0); + re1 : in std_ulogic; + rdata1 : out std_logic_vector((dbits -1) downto 0); + raddr2 : in std_logic_vector((abits -1) downto 0); + re2 : in std_ulogic; + rdata2 : out std_logic_vector((dbits -1) downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + +-- 64-bit synchronous single-port ram with 32-bit write strobe + component syncram64 + generic (tech : integer := 0; abits : integer := 6; testen : integer := 0); + port ( + clk : in std_ulogic; + address : in std_logic_vector (abits -1 downto 0); + datain : in std_logic_vector (63 downto 0); + dataout : out std_logic_vector (63 downto 0); + enable : in std_logic_vector (1 downto 0); + write : in std_logic_vector (1 downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + + component syncramft + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + ft : integer range 0 to 2 := 0 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + write : in std_ulogic; + enable : in std_ulogic; + error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + + component syncram_2pft + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); + end component; + + component syncfifo + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0); + port ( + rst : in std_ulogic; + rclk : in std_ulogic; + renable : in std_ulogic; + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + datain : in std_logic_vector((dbits -1) downto 0); + full : out std_ulogic; + empty : out std_ulogic + ); + end component; + + +--------------------------------------------------------------------------- +-- PADS +--------------------------------------------------------------------------- + +component inpad + generic (tech : integer := 0; level : integer := 0; + voltage : integer := x33v; filter : integer := 0; + strength : integer := 0); + port (pad : in std_ulogic; o : out std_ulogic); +end component; + +component inpadv + generic (tech : integer := 0; level : integer := 0; + voltage : integer := x33v; width : integer := 1); + port ( + pad : in std_logic_vector(width-1 downto 0); + o : out std_logic_vector(width-1 downto 0)); +end component; + +component iopad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0; filter : integer := 0); + port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic); +end component; + +component iopadv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : inout std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_ulogic; + o : out std_logic_vector(width-1 downto 0)); +end component; + +component iopadvv is + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : inout std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_logic_vector(width-1 downto 0); + o : out std_logic_vector(width-1 downto 0)); +end component; + +component iodpad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic); +end component; + +component iodpadv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : inout std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + o : out std_logic_vector(width-1 downto 0)); +end component; + +component outpad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12); + port (pad : out std_ulogic; i : in std_ulogic); +end component; + +component outpadv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1); + port ( + pad : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0)); +end component; + +component odpad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (pad : out std_ulogic; i : in std_ulogic); +end component; + +component odpadv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0)); +end component; + +component toutpad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (pad : out std_ulogic; i, en : in std_ulogic); +end component; + +component toutpadv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_ulogic); +end component; + +component toutpadvv is + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + pad : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_logic_vector(width-1 downto 0)); +end component; + +component toutpad_ds + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (padp, padn : out std_ulogic; i, en : in std_ulogic); +end component; + +component toutpad_dsv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + padp : out std_logic_vector(width-1 downto 0); + padn : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_ulogic); +end component; + +component toutpad_dsvv is + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port ( + padp : out std_logic_vector(width-1 downto 0); + padn : out std_logic_vector(width-1 downto 0); + i : in std_logic_vector(width-1 downto 0); + en : in std_logic_vector(width-1 downto 0)); +end component; + +component skew_outpad + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; skew : integer := 0); + port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic; + o : out std_ulogic); +end component; + +component clkpad + generic (tech : integer := 0; level : integer := 0; + voltage : integer := x33v; arch : integer := 0; hf : integer := 0); + port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic); +end component; + +component inpad_ds + generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v); + port (padp, padn : in std_ulogic; o : out std_ulogic); +end component; + +component clkpad_ds + generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v); + port (padp, padn : in std_ulogic; o : out std_ulogic); +end component; + +component inpad_dsv + generic (tech : integer := 0; level : integer := lvds; + voltage : integer := x33v; width : integer := 1); + port ( + padp : in std_logic_vector(width-1 downto 0); + padn : in std_logic_vector(width-1 downto 0); + o : out std_logic_vector(width-1 downto 0)); +end component; + +component iopad_ds + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic); +end component; + +component outpad_ds + generic (tech : integer := 0; level : integer := lvds; + voltage : integer := x33v; oepol : integer := 0); + port (padp, padn : out std_ulogic; i, en : in std_ulogic); +end component; + +component outpad_dsv + generic (tech : integer := 0; level : integer := lvds; + voltage : integer := x33v; width : integer := 1); + port ( + padp : out std_logic_vector(width-1 downto 0); + padn : out std_logic_vector(width-1 downto 0); + i, en: in std_logic_vector(width-1 downto 0)); +end component; + +component lvds_combo is + generic (tech : integer := 0; voltage : integer := 0; width : integer := 1; + oepol : integer := 0); + port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1); + odval, osval, en : in std_logic_vector(0 to width-1); + idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1); + idval, isval : out std_logic_vector(0 to width-1); + lvdsref : in std_logic := '1' + ); +end component; + +------------------------------------------------------------------------------- +-- DDR PADS (bundles PAD and DDR register(s)) +------------------------------------------------------------------------------- + +component inpad_ddr + generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v; + filter : integer := 0; strength : integer := 0 ); + port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; + ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); +end component; + +component inpad_ddrv + generic (tech : integer := 0; level : integer := 0; voltage : integer := 0; + filter : integer := 0; strength : integer := 0; width : integer := 1); + port (pad : in std_logic_vector(width-1 downto 0); + o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; + ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic); +end component; + +component outpad_ddr + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12); + port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic; + ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); +end component; + +component outpad_ddrv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := 0; strength : integer := 12; + width : integer := 1); + port (pad : out std_logic_vector(width-1 downto 0); + i1, i2 : in std_logic_vector(width-1 downto 0); + c1, c2 : in std_ulogic; ce : in std_ulogic; + r : in std_ulogic; s : in std_ulogic); +end component; + +component iopad_ddr + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; + oepol : integer := 0); + port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic; + o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic; + r : in std_ulogic; s : in std_ulogic); +end component; + +component iopad_ddrv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port (pad : inout std_logic_vector(width-1 downto 0); + i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic; + o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; + ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); +end component; + +component iopad_ddrvv + generic (tech : integer := 0; level : integer := 0; slew : integer := 0; + voltage : integer := x33v; strength : integer := 12; width : integer := 1; + oepol : integer := 0); + port (pad : inout std_logic_vector(width-1 downto 0); + i1, i2 : in std_logic_vector(width-1 downto 0); + en : in std_logic_vector(width-1 downto 0); + o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; + ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic); +end component; + +--------------------------------------------------------------------------- +-- BUFFERS +--------------------------------------------------------------------------- + + component techbuf is + generic( + buftype : integer range 0 to 4 := 0; + tech : integer range 0 to NTECH := inferred); + port( + i : in std_ulogic; + o : out std_ulogic + ); + end component; + +--------------------------------------------------------------------------- +-- CLOCK GENERATION +--------------------------------------------------------------------------- + +type clkgen_in_type is record + pllref : std_logic; -- optional reference for PLL + pllrst : std_logic; -- optional reset for PLL + pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL + clksel : std_logic_vector(1 downto 0); -- optional clock select +end record; + +type clkgen_out_type is record + clklock : std_logic; + pcilock : std_logic; +end record; + +component clkgen + generic ( + tech : integer := DEFFABTECH; + clk_mul : integer := 1; + clk_div : integer := 1; + sdramen : integer := 0; + noclkfb : integer := 1; + pcien : integer := 0; + pcidll : integer := 0; + pcisysclk: integer := 0; + freq : integer := 25000; + clk2xen : integer := 0; + clksel : integer := 0; -- enable clock select + clk_odiv : integer := 0); -- Proasic3 output divider +port ( + clkin : in std_logic; + pciclkin: in std_logic; + clk : out std_logic; -- main clock + clkn : out std_logic; -- inverted main clock + clk2x : out std_logic; -- 2x clock + sdclk : out std_logic; -- SDRAM clock + pciclk : out std_logic; -- PCI clock + cgi : in clkgen_in_type; + cgo : out clkgen_out_type; + clk4x : out std_logic; -- 4x clock + clk1xu : out std_logic; -- unscaled 1X clock + clk2xu : out std_logic); -- unscaled 2X clock +end component; + +component clkand + generic( tech : integer := 0; + ren : integer range 0 to 1 := 0); -- registered enable + port( + i : in std_ulogic; + en : in std_ulogic; + o : out std_ulogic; + tsten : in std_ulogic := '0' + ); +end component; + +component clkmux + generic( tech : integer := 0; + rsel : integer range 0 to 1 := 0); -- registered sel + port( + i0, i1 : in std_ulogic; + sel : in std_ulogic; + o : out std_ulogic; + rst : in std_ulogic := '1' + ); +end component; + + + + +--------------------------------------------------------------------------- +-- TAP controller +--------------------------------------------------------------------------- + +component tap + generic ( + tech : integer := 0; + irlen : integer range 2 to 8 := 4; + idcode : integer range 0 to 255 := 9; + manf : integer range 0 to 2047 := 804; + part : integer range 0 to 65535 := 0; + ver : integer range 0 to 15 := 0; + trsten : integer range 0 to 1 := 1; + scantest : integer := 0); + port ( + trst : in std_ulogic; + tck : in std_ulogic; + tms : in std_ulogic; + tdi : in std_ulogic; + tdo : out std_ulogic; + tapo_tck : out std_ulogic; + tapo_tdi : out std_ulogic; + tapo_inst : out std_logic_vector(7 downto 0); + tapo_rst : out std_ulogic; + tapo_capt : out std_ulogic; + tapo_shft : out std_ulogic; + tapo_upd : out std_ulogic; + tapo_xsel1 : out std_ulogic; + tapo_xsel2 : out std_ulogic; + tapi_en1 : in std_ulogic; + tapi_tdo1 : in std_ulogic; + tapi_tdo2 : in std_ulogic; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1'; + tdoen : out std_ulogic + ); +end component; + +--------------------------------------------------------------------------- +-- DDR registers and PHY +--------------------------------------------------------------------------- + +component ddr_ireg is +generic ( tech : integer); +port ( Q1 : out std_ulogic; + Q2 : out std_ulogic; + C1 : in std_ulogic; + C2 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic); +end component; + +component ddr_oreg is generic ( tech : integer); + port + ( Q : out std_ulogic; + C1 : in std_ulogic; + C2 : in std_ulogic; + CE : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic); +end component; + +component ddrphy + generic (tech : integer := virtex2; MHz : integer := 100; + rstdelay : integer := 200; dbits : integer := 16; + clk_mul : integer := 2 ; clk_div : integer := 2; + rskew : integer :=0; mobile : integer := 0); + port ( + rst : in std_ulogic; + clk : in std_logic; -- input clock + clkout : out std_ulogic; -- system clock + clkread : out std_ulogic; -- read clock + lock : out std_ulogic; -- DCM locked + ddr_clk : out std_logic_vector(2 downto 0); + ddr_clkb : out std_logic_vector(2 downto 0); + ddr_clk_fb_out : out std_logic; + ddr_clk_fb : in std_logic; + ddr_cke : out std_logic_vector(1 downto 0); + ddr_csb : out std_logic_vector(1 downto 0); + ddr_web : out std_ulogic; -- ddr write enable + ddr_rasb : out std_ulogic; -- ddr ras + ddr_casb : out std_ulogic; -- ddr cas + ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm + ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs + ddr_ad : out std_logic_vector (13 downto 0); -- ddr address + ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address + ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data + + addr : in std_logic_vector (13 downto 0); -- data mask + ba : in std_logic_vector ( 1 downto 0); -- data mask + dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data + dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data + dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask + oen : in std_ulogic; + dqs : in std_ulogic; + dqsoen : in std_ulogic; + rasn : in std_ulogic; + casn : in std_ulogic; + wen : in std_ulogic; + csn : in std_logic_vector(1 downto 0); + cke : in std_logic_vector(1 downto 0); + ck : in std_logic_vector(2 downto 0); + moben : in std_logic); +end component; + +component ddr2phy + generic ( + tech : integer := virtex5; MHz : integer := 100; + rstdelay : integer := 200; dbits : integer := 16; + clk_mul : integer := 2; clk_div : integer := 2; + ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0; + ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0; + ddelayb6 : integer := 0; ddelayb7 : integer := 0; + numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0; + eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0); + port ( + rst : in std_ulogic; + clk : in std_logic; -- input clock + clkref200 : in std_logic; -- input 200MHz clock + clkout : out std_ulogic; -- system clock + lock : out std_ulogic; -- DCM locked + + ddr_clk : out std_logic_vector(2 downto 0); + ddr_clkb : out std_logic_vector(2 downto 0); + ddr_clk_fb_out : out std_logic; + ddr_clk_fb : in std_logic; + ddr_cke : out std_logic_vector(1 downto 0); + ddr_csb : out std_logic_vector(1 downto 0); + ddr_web : out std_ulogic; -- ddr write enable + ddr_rasb : out std_ulogic; -- ddr ras + ddr_casb : out std_ulogic; -- ddr cas + ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm + ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs + ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn + ddr_ad : out std_logic_vector (13 downto 0); -- ddr address + ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address + ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data + ddr_odt : out std_logic_vector(1 downto 0); + + addr : in std_logic_vector (13 downto 0); + ba : in std_logic_vector ( 2 downto 0); + dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data + dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data + dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask + oen : in std_ulogic; + dqs : in std_ulogic; + dqsoen : in std_ulogic; + rasn : in std_ulogic; + casn : in std_ulogic; + wen : in std_ulogic; + csn : in std_logic_vector(1 downto 0); + cke : in std_logic_vector(1 downto 0); + cal_en : in std_logic_vector(dbits/8-1 downto 0); + cal_inc : in std_logic_vector(dbits/8-1 downto 0); + cal_pll : in std_logic_vector(1 downto 0); + cal_rst : in std_logic; + odt : in std_logic_vector(1 downto 0); + oct : in std_logic; + dqs_gate : in std_ulogic + ); +end component; + +--------------------------------------------------------------------------- +-- 61x61 Multiplier +--------------------------------------------------------------------------- + +component mul_61x61 + generic (multech : integer := 0; + fabtech : integer := 0); + port(A : in std_logic_vector(60 downto 0); + B : in std_logic_vector(60 downto 0); + EN : in std_logic; + CLK : in std_logic; + PRODUCT : out std_logic_vector(121 downto 0)); +end component; + +--------------------------------------------------------------------------- +-- Ring oscillator +--------------------------------------------------------------------------- + + component ringosc + generic (tech : integer := 0); + port ( + roen : in Std_ULogic; + roout : out Std_ULogic); + end component; + +--------------------------------------------------------------------------- +-- System monitor +--------------------------------------------------------------------------- + +component system_monitor + generic ( + -- GRLIB generics + tech : integer := DEFFABTECH; + -- Virtex 5 SYSMON generics + INIT_40 : bit_vector := X"0000"; + INIT_41 : bit_vector := X"0000"; + INIT_42 : bit_vector := X"0800"; + INIT_43 : bit_vector := X"0000"; + INIT_44 : bit_vector := X"0000"; + INIT_45 : bit_vector := X"0000"; + INIT_46 : bit_vector := X"0000"; + INIT_47 : bit_vector := X"0000"; + INIT_48 : bit_vector := X"0000"; + INIT_49 : bit_vector := X"0000"; + INIT_4A : bit_vector := X"0000"; + INIT_4B : bit_vector := X"0000"; + INIT_4C : bit_vector := X"0000"; + INIT_4D : bit_vector := X"0000"; + INIT_4E : bit_vector := X"0000"; + INIT_4F : bit_vector := X"0000"; + INIT_50 : bit_vector := X"0000"; + INIT_51 : bit_vector := X"0000"; + INIT_52 : bit_vector := X"0000"; + INIT_53 : bit_vector := X"0000"; + INIT_54 : bit_vector := X"0000"; + INIT_55 : bit_vector := X"0000"; + INIT_56 : bit_vector := X"0000"; + INIT_57 : bit_vector := X"0000"; + SIM_MONITOR_FILE : string := "design.txt"); + port ( + alm : out std_logic_vector(2 downto 0); + busy : out std_ulogic; + channel : out std_logic_vector(4 downto 0); + do : out std_logic_vector(15 downto 0); + drdy : out std_ulogic; + eoc : out std_ulogic; + eos : out std_ulogic; + jtagbusy : out std_ulogic; + jtaglocked : out std_ulogic; + jtagmodified : out std_ulogic; + ot : out std_ulogic; + convst : in std_ulogic; + convstclk : in std_ulogic; + daddr : in std_logic_vector(6 downto 0); + dclk : in std_ulogic; + den : in std_ulogic; + di : in std_logic_vector(15 downto 0); + dwe : in std_ulogic; + reset : in std_ulogic; + vauxn : in std_logic_vector(15 downto 0); + vauxp : in std_logic_vector(15 downto 0); + vn : in std_ulogic; + vp : in std_ulogic); +end component; + + +component nandtree + generic( + tech : integer := inferred; + width : integer := 2; + imp : integer := 0 ); + port( i : in std_logic_vector(width-1 downto 0); + o : out std_ulogic; + en : in std_ulogic + ); +end component; + +component grmux2 is generic( tech : integer := inferred; imp : integer := 0); + port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component; + +end; + diff --git a/techmap/rtl/memory_inferred.vhd b/techmap/rtl/memory_inferred.vhd new file mode 100644 index 0000000..b540f32 --- /dev/null +++ b/techmap/rtl/memory_inferred.vhd @@ -0,0 +1,279 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2010, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: various +-- File: mem_gen_gen.vhd +-- Author: Jiri Gaisler Gaisler Research +-- Description: Behavioural memory generators +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; + +entity generic_syncram is + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + write : in std_ulogic + ); +end; + +architecture behavioral of generic_syncram is + + type mem is array(0 to (2**abits -1)) + of std_logic_vector((dbits -1) downto 0); + signal memarr : mem; + signal ra : std_logic_vector((abits -1) downto 0); + +begin + + main : process(clk) + begin + if rising_edge(clk) then + if write = '1' then + memarr(conv_integer(address)) <= datain; + end if; + ra <= address; + end if; + end process; + + dataout <= memarr(conv_integer(ra)); + +end; + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; + +entity generic_syncram_reg is + generic ( abits : integer := 10; dbits : integer := 8 ); + port ( + clk : in std_ulogic; + address : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + write : in std_ulogic + ); +end; + +architecture behavioral of generic_syncram_reg is + + type mem is array(0 to (2**abits -1)) + of std_logic_vector((dbits -1) downto 0); + signal memarr : mem; + signal ra : std_logic_vector((abits -1) downto 0); + + attribute syn_ramstyle : string; + attribute syn_ramstyle of memarr : signal is "registers"; +begin + + main : process(clk) + begin + if rising_edge(clk) then + if write = '1' then + memarr(conv_integer(address)) <= datain; + end if; + ra <= address; + end if; + end process; + + dataout <= memarr(conv_integer(ra)); + +end; + +-- synchronous 2-port ram, common clock + +LIBRARY ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; + +entity generic_syncram_2p is + generic ( + abits : integer := 8; + dbits : integer := 32; + sepclk: integer := 0 + ); + port ( + rclk : in std_ulogic; + wclk : in std_ulogic; + rdaddress: in std_logic_vector (abits -1 downto 0); + wraddress: in std_logic_vector (abits -1 downto 0); + data: in std_logic_vector (dbits -1 downto 0); + wren : in std_ulogic; + q: out std_logic_vector (dbits -1 downto 0) + ); +end; + +architecture behav of generic_syncram_2p is + type dregtype is array (0 to 2**abits - 1) + of std_logic_vector(dbits -1 downto 0); + signal rfd : dregtype; + signal wa, ra : std_logic_vector (abits -1 downto 0); +begin + + wp : process(wclk) + begin + if rising_edge(wclk) then + if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if; + end if; + end process; + + oneclk : if sepclk = 0 generate + rp : process(wclk) begin + if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if; + end process; + end generate; + + twoclk : if sepclk = 1 generate + rp : process(rclk) begin + if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if; + end process; + end generate; + +end; + + +-- synchronous 2-port ram, common clock, flip-flops + +LIBRARY ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; + +entity generic_syncram_2p_reg is + generic ( + abits : integer := 8; + dbits : integer := 32; + sepclk: integer := 0 + ); + port ( + rclk : in std_ulogic; + wclk : in std_ulogic; + rdaddress: in std_logic_vector (abits -1 downto 0); + wraddress: in std_logic_vector (abits -1 downto 0); + data: in std_logic_vector (dbits -1 downto 0); + wren : in std_ulogic; + q: out std_logic_vector (dbits -1 downto 0) + ); +end; + +architecture behav of generic_syncram_2p_reg is + type dregtype is array (0 to 2**abits - 1) + of std_logic_vector(dbits -1 downto 0); + signal rfd : dregtype; + signal wa, ra : std_logic_vector (abits -1 downto 0); + attribute syn_ramstyle : string; + attribute syn_ramstyle of rfd : signal is "registers"; +begin + + wp : process(wclk) + begin + if rising_edge(wclk) then + if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if; + end if; + end process; + + oneclk : if sepclk = 0 generate + rp : process(wclk) begin + if rising_edge(wclk) then ra <= rdaddress; end if; + end process; + end generate; + + twoclk : if sepclk = 1 generate + rp : process(rclk) begin + if rising_edge(rclk) then ra <= rdaddress; end if; + end process; + end generate; + + q <= rfd(conv_integer(ra)); + +end; + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; + +entity generic_regfile_3p is + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32; + wrfst : integer := 0; numregs : integer := 40); + port ( + wclk : in std_ulogic; + waddr : in std_logic_vector((abits -1) downto 0); + wdata : in std_logic_vector((dbits -1) downto 0); + we : in std_ulogic; + rclk : in std_ulogic; + raddr1 : in std_logic_vector((abits -1) downto 0); + re1 : in std_ulogic; + rdata1 : out std_logic_vector((dbits -1) downto 0); + raddr2 : in std_logic_vector((abits -1) downto 0); + re2 : in std_ulogic; + rdata2 : out std_logic_vector((dbits -1) downto 0) + ); +end; + +architecture rtl of generic_regfile_3p is + type mem is array(0 to numregs-1) + of std_logic_vector((dbits -1) downto 0); + signal memarr : mem; + signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0); + signal din : std_logic_vector((dbits -1) downto 0); + signal wr : std_ulogic; + +begin + + main : process(wclk) + begin + if rising_edge(wclk) then + din <= wdata; wr <= we; + if (we = '1') +-- pragma translate_off + and (conv_integer(waddr) < numregs) +-- pragma translate_on + then wa <= waddr; end if; + if (re1 = '1') +-- pragma translate_off + and (conv_integer(raddr1) < numregs) +-- pragma translate_on + then ra1 <= raddr1; end if; + if (re2 = '1') +-- pragma translate_off + and (conv_integer(raddr2) < numregs) +-- pragma translate_on + then ra2 <= raddr2; end if; + if wr = '1' then + memarr(conv_integer(wa)) <= din; + end if; + end if; + end process; + + rdata1 <= din when (wr = '1') and (wa = ra1) and (wrfst = 1) + else memarr(conv_integer(ra1)); + rdata2 <= din when (wr = '1') and (wa = ra2) and (wrfst = 1) + else memarr(conv_integer(ra2)); + +end; + diff --git a/techmap/rtl/netcomp.vhd b/techmap/rtl/netcomp.vhd new file mode 100644 index 0000000..415bd49 --- /dev/null +++ b/techmap/rtl/netcomp.vhd @@ -0,0 +1,816 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2010, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Package: netcomp +-- File: netcomp.vhd +-- Author: Jiri Gaisler - Aeroflex Gaisler +-- Description: Declaration of netlists components +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use work.gencomp.all; + +package netcomp is + +--------------------------------------------------------------------------- +-- netlists --------------------------------------------------------------- +--------------------------------------------------------------------------- + +component grusbhc_net is + generic ( + tech : integer := 0; + nports : integer range 1 to 15 := 1; + ehcgen : integer range 0 to 1 := 1; + uhcgen : integer range 0 to 1 := 1; + n_cc : integer range 1 to 15 := 1; + n_pcc : integer range 1 to 15 := 1; + prr : integer range 0 to 1 := 0; + portroute1 : integer := 0; + portroute2 : integer := 0; + endian_conv : integer range 0 to 1 := 1; + be_regs : integer range 0 to 1 := 0; + be_desc : integer range 0 to 1 := 0; + uhcblo : integer range 0 to 255 := 2; + bwrd : integer range 1 to 256 := 16; + utm_type : integer range 0 to 2 := 2; + vbusconf : integer := 3; + ramtest : integer range 0 to 1 := 0; + urst_time : integer := 250; + oepol : integer range 0 to 1 := 0; + scantest : integer range 0 to 1 := 0; + memtech : integer range 0 to NTECH := DEFMEMTECH; + memsel : integer := 0; + syncprst : integer range 0 to 1 := 0; + sysfreq : integer := 65000); + port ( + clk : in std_ulogic; + uclk : in std_ulogic; + rst : in std_ulogic; + -- EHC apb_slv_in_type unwrapped + ehc_apbsi_psel : in std_ulogic; + ehc_apbsi_penable : in std_ulogic; + ehc_apbsi_paddr : in std_logic_vector(31 downto 0); + ehc_apbsi_pwrite : in std_ulogic; + ehc_apbsi_pwdata : in std_logic_vector(31 downto 0); + -- EHC apb_slv_out_type unwrapped + ehc_apbso_prdata : out std_logic_vector(31 downto 0); + ehc_apbso_pirq : out std_ulogic; + -- EHC/UHC ahb_mst_in_type unwrapped + ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0); + ahbmi_hready : in std_ulogic; + ahbmi_hresp : in std_logic_vector(1 downto 0); + ahbmi_hrdata : in std_logic_vector(31 downto 0); + ahbmi_hcache : in std_ulogic; + -- UHC ahb_slv_in_type unwrapped + uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbsi_haddr : in std_logic_vector(31 downto 0); + uhc_ahbsi_hwrite : in std_ulogic; + uhc_ahbsi_htrans : in std_logic_vector(1 downto 0); + uhc_ahbsi_hsize : in std_logic_vector(2 downto 0); + uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0); + uhc_ahbsi_hready : in std_ulogic; + -- EHC ahb_mst_out_type_unwrapped + ehc_ahbmo_hbusreq : out std_ulogic; + ehc_ahbmo_hlock : out std_ulogic; + ehc_ahbmo_htrans : out std_logic_vector(1 downto 0); + ehc_ahbmo_haddr : out std_logic_vector(31 downto 0); + ehc_ahbmo_hwrite : out std_ulogic; + ehc_ahbmo_hsize : out std_logic_vector(2 downto 0); + ehc_ahbmo_hburst : out std_logic_vector(2 downto 0); + ehc_ahbmo_hprot : out std_logic_vector(3 downto 0); + ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0); + -- UHC ahb_mst_out_vector_type unwrapped + uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen); + uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen); + uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen); + uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen); + uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + -- UHC ahb_slv_out_vector_type unwrapped + uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen); + uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen); + uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + -- grusb_out_type_vector unwrapped + xcvrsel : out std_logic_vector(((nports*2)-1) downto 0); + termsel : out std_logic_vector((nports-1) downto 0); + opmode : out std_logic_vector(((nports*2)-1) downto 0); + txvalid : out std_logic_vector((nports-1) downto 0); + drvvbus : out std_logic_vector((nports-1) downto 0); + dataho : out std_logic_vector(((nports*8)-1) downto 0); + validho : out std_logic_vector((nports-1) downto 0); + stp : out std_logic_vector((nports-1) downto 0); + datao : out std_logic_vector(((nports*8)-1) downto 0); + utm_rst : out std_logic_vector((nports-1) downto 0); + dctrlo : out std_logic_vector((nports-1) downto 0); + suspendm : out std_ulogic; + dbus16_8 : out std_ulogic; + dppulldown : out std_ulogic; + dmpulldown : out std_ulogic; + idpullup : out std_ulogic; + dischrgvbus : out std_ulogic; + chrgvbus : out std_ulogic; + txbitstuffenable : out std_ulogic; + txbitstuffenableh : out std_ulogic; + fslsserialmode : out std_ulogic; + txenablen : out std_ulogic; + txdat : out std_ulogic; + txse0 : out std_ulogic; + -- grusb_in_type_vector unwrapped + linestate : in std_logic_vector(((nports*2)-1) downto 0); + txready : in std_logic_vector((nports-1) downto 0); + rxvalid : in std_logic_vector((nports-1) downto 0); + rxactive : in std_logic_vector((nports-1) downto 0); + rxerror : in std_logic_vector((nports-1) downto 0); + vbusvalid : in std_logic_vector((nports-1) downto 0); + datahi : in std_logic_vector(((nports*8)-1) downto 0); + validhi : in std_logic_vector((nports-1) downto 0); + hostdisc : in std_logic_vector((nports-1) downto 0); + nxt : in std_logic_vector((nports-1) downto 0); + dir : in std_logic_vector((nports-1) downto 0); + datai : in std_logic_vector(((nports*8)-1) downto 0); + urstdrive : in std_logic_vector((nports-1) downto 0); + -- EHC transaction buffer signals + mbc20_tb_addr : out std_logic_vector(8 downto 0); + mbc20_tb_data : out std_logic_vector(31 downto 0); + mbc20_tb_en : out std_ulogic; + mbc20_tb_wel : out std_ulogic; + mbc20_tb_weh : out std_ulogic; + tb_mbc20_data : in std_logic_vector(31 downto 0); + pe20_tb_addr : out std_logic_vector(8 downto 0); + pe20_tb_data : out std_logic_vector(31 downto 0); + pe20_tb_en : out std_ulogic; + pe20_tb_wel : out std_ulogic; + pe20_tb_weh : out std_ulogic; + tb_pe20_data : in std_logic_vector(31 downto 0); + -- EHC packet buffer signals + mbc20_pb_addr : out std_logic_vector(8 downto 0); + mbc20_pb_data : out std_logic_vector(31 downto 0); + mbc20_pb_en : out std_ulogic; + mbc20_pb_we : out std_ulogic; + pb_mbc20_data : in std_logic_vector(31 downto 0); + sie20_pb_addr : out std_logic_vector(8 downto 0); + sie20_pb_data : out std_logic_vector(31 downto 0); + sie20_pb_en : out std_ulogic; + sie20_pb_we : out std_ulogic; + pb_sie20_data : in std_logic_vector(31 downto 0); + -- UHC packet buffer signals + sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen); + sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen); + mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); + pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); + bufsel : out std_ulogic; + -- scan signals + testen : in std_ulogic; + testrst : in std_ulogic; + scanen : in std_ulogic; + testoen : in std_ulogic); + end component; + +component grspwc_net + generic( + tech : integer := 0; + sysfreq : integer := 40000; + usegen : integer range 0 to 1 := 1; + nsync : integer range 1 to 2 := 1; + rmap : integer range 0 to 1 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 32 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0 + ); + port( + rst : in std_ulogic; + clk : in std_ulogic; + txclk : in std_ulogic; + --ahb mst in + hgrant : in std_ulogic; + hready : in std_ulogic; + hresp : in std_logic_vector(1 downto 0); + hrdata : in std_logic_vector(31 downto 0); + --ahb mst out + hbusreq : out std_ulogic; + hlock : out std_ulogic; + htrans : out std_logic_vector(1 downto 0); + haddr : out std_logic_vector(31 downto 0); + hwrite : out std_ulogic; + hsize : out std_logic_vector(2 downto 0); + hburst : out std_logic_vector(2 downto 0); + hprot : out std_logic_vector(3 downto 0); + hwdata : out std_logic_vector(31 downto 0); + --apb slv in + psel : in std_ulogic; + penable : in std_ulogic; + paddr : in std_logic_vector(31 downto 0); + pwrite : in std_ulogic; + pwdata : in std_logic_vector(31 downto 0); + --apb slv out + prdata : out std_logic_vector(31 downto 0); + --spw in + di : in std_logic_vector(1 downto 0); + si : in std_logic_vector(1 downto 0); + --spw out + do : out std_logic_vector(1 downto 0); + so : out std_logic_vector(1 downto 0); + --time iface + tickin : in std_ulogic; + tickout : out std_ulogic; + --irq + irq : out std_logic; + --misc + clkdiv10 : in std_logic_vector(7 downto 0); + dcrstval : in std_logic_vector(9 downto 0); + timerrstval : in std_logic_vector(11 downto 0); + --rmapen + rmapen : in std_ulogic; + --clk bufs + rxclki : in std_logic_vector(1 downto 0); + nrxclki : in std_logic_vector(1 downto 0); + rxclko : out std_logic_vector(1 downto 0); + --rx ahb fifo + rxrenable : out std_ulogic; + rxraddress : out std_logic_vector(4 downto 0); + rxwrite : out std_ulogic; + rxwdata : out std_logic_vector(31 downto 0); + rxwaddress : out std_logic_vector(4 downto 0); + rxrdata : in std_logic_vector(31 downto 0); + --tx ahb fifo + txrenable : out std_ulogic; + txraddress : out std_logic_vector(4 downto 0); + txwrite : out std_ulogic; + txwdata : out std_logic_vector(31 downto 0); + txwaddress : out std_logic_vector(4 downto 0); + txrdata : in std_logic_vector(31 downto 0); + --nchar fifo + ncrenable : out std_ulogic; + ncraddress : out std_logic_vector(5 downto 0); + ncwrite : out std_ulogic; + ncwdata : out std_logic_vector(8 downto 0); + ncwaddress : out std_logic_vector(5 downto 0); + ncrdata : in std_logic_vector(8 downto 0); + --rmap buf + rmrenable : out std_ulogic; + rmraddress : out std_logic_vector(7 downto 0); + rmwrite : out std_ulogic; + rmwdata : out std_logic_vector(7 downto 0); + rmwaddress : out std_logic_vector(7 downto 0); + rmrdata : in std_logic_vector(7 downto 0); + linkdis : out std_ulogic; + testclk : in std_ulogic := '0'; + testrst : in std_ulogic := '0'; + testen : in std_ulogic := '0' + ); +end component; + +component grspwc2_net + generic( + rmap : integer range 0 to 1 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 32 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + tech : integer; + input_type : integer range 0 to 3 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0 + ); + port( + rst : in std_ulogic; + clk : in std_ulogic; + rxclk : in std_logic_vector(1 downto 0); + txclk : in std_ulogic; + txclkn : in std_ulogic; + --ahb mst in + hgrant : in std_ulogic; + hready : in std_ulogic; + hresp : in std_logic_vector(1 downto 0); + hrdata : in std_logic_vector(31 downto 0); + --ahb mst out + hbusreq : out std_ulogic; + hlock : out std_ulogic; + htrans : out std_logic_vector(1 downto 0); + haddr : out std_logic_vector(31 downto 0); + hwrite : out std_ulogic; + hsize : out std_logic_vector(2 downto 0); + hburst : out std_logic_vector(2 downto 0); + hprot : out std_logic_vector(3 downto 0); + hwdata : out std_logic_vector(31 downto 0); + --apb slv in + psel : in std_ulogic; + penable : in std_ulogic; + paddr : in std_logic_vector(31 downto 0); + pwrite : in std_ulogic; + pwdata : in std_logic_vector(31 downto 0); + --apb slv out + prdata : out std_logic_vector(31 downto 0); + --spw in + d : in std_logic_vector(3 downto 0); + dv : in std_logic_vector(3 downto 0); + dconnect : in std_logic_vector(3 downto 0); + --spw out + do : out std_logic_vector(3 downto 0); + so : out std_logic_vector(3 downto 0); + --time iface + tickin : in std_ulogic; + tickout : out std_ulogic; + --irq + irq : out std_logic; + --misc + clkdiv10 : in std_logic_vector(7 downto 0); + dcrstval : in std_logic_vector(9 downto 0); + timerrstval : in std_logic_vector(11 downto 0); + --rmapen + rmapen : in std_ulogic; + --rx ahb fifo + rxrenable : out std_ulogic; + rxraddress : out std_logic_vector(4 downto 0); + rxwrite : out std_ulogic; + rxwdata : out std_logic_vector(31 downto 0); + rxwaddress : out std_logic_vector(4 downto 0); + rxrdata : in std_logic_vector(31 downto 0); + --tx ahb fifo + txrenable : out std_ulogic; + txraddress : out std_logic_vector(4 downto 0); + txwrite : out std_ulogic; + txwdata : out std_logic_vector(31 downto 0); + txwaddress : out std_logic_vector(4 downto 0); + txrdata : in std_logic_vector(31 downto 0); + --nchar fifo + ncrenable : out std_ulogic; + ncraddress : out std_logic_vector(5 downto 0); + ncwrite : out std_ulogic; + ncwdata : out std_logic_vector(9 downto 0); + ncwaddress : out std_logic_vector(5 downto 0); + ncrdata : in std_logic_vector(9 downto 0); + --rmap buf + rmrenable : out std_ulogic; + rmraddress : out std_logic_vector(7 downto 0); + rmwrite : out std_ulogic; + rmwdata : out std_logic_vector(7 downto 0); + rmwaddress : out std_logic_vector(7 downto 0); + rmrdata : in std_logic_vector(7 downto 0); + linkdis : out std_ulogic; + testclk : in std_ulogic := '0'; + testrst : in std_ulogic := '0'; + testen : in std_ulogic := '0' + ); +end component; + + component grlfpw_net + generic (tech : integer := 0; + pclow : integer range 0 to 2 := 2; + dsu : integer range 0 to 1 := 1; + disas : integer range 0 to 2 := 0; + pipe : integer range 0 to 2 := 0 + ); + port ( + rst : in std_ulogic; -- Reset + clk : in std_ulogic; + holdn : in std_ulogic; -- pipeline hold + cpi_flush : in std_ulogic; -- pipeline flush + cpi_exack : in std_ulogic; -- FP exception acknowledge + cpi_a_rs1 : in std_logic_vector(4 downto 0); + cpi_d_pc : in std_logic_vector(31 downto 0); + cpi_d_inst : in std_logic_vector(31 downto 0); + cpi_d_cnt : in std_logic_vector(1 downto 0); + cpi_d_trap : in std_ulogic; + cpi_d_annul : in std_ulogic; + cpi_d_pv : in std_ulogic; + cpi_a_pc : in std_logic_vector(31 downto 0); + cpi_a_inst : in std_logic_vector(31 downto 0); + cpi_a_cnt : in std_logic_vector(1 downto 0); + cpi_a_trap : in std_ulogic; + cpi_a_annul : in std_ulogic; + cpi_a_pv : in std_ulogic; + cpi_e_pc : in std_logic_vector(31 downto 0); + cpi_e_inst : in std_logic_vector(31 downto 0); + cpi_e_cnt : in std_logic_vector(1 downto 0); + cpi_e_trap : in std_ulogic; + cpi_e_annul : in std_ulogic; + cpi_e_pv : in std_ulogic; + cpi_m_pc : in std_logic_vector(31 downto 0); + cpi_m_inst : in std_logic_vector(31 downto 0); + cpi_m_cnt : in std_logic_vector(1 downto 0); + cpi_m_trap : in std_ulogic; + cpi_m_annul : in std_ulogic; + cpi_m_pv : in std_ulogic; + cpi_x_pc : in std_logic_vector(31 downto 0); + cpi_x_inst : in std_logic_vector(31 downto 0); + cpi_x_cnt : in std_logic_vector(1 downto 0); + cpi_x_trap : in std_ulogic; + cpi_x_annul : in std_ulogic; + cpi_x_pv : in std_ulogic; + cpi_lddata : in std_logic_vector(31 downto 0); -- load data + cpi_dbg_enable : in std_ulogic; + cpi_dbg_write : in std_ulogic; + cpi_dbg_fsr : in std_ulogic; -- FSR access + cpi_dbg_addr : in std_logic_vector(4 downto 0); + cpi_dbg_data : in std_logic_vector(31 downto 0); + cpo_data : out std_logic_vector(31 downto 0); -- store data + cpo_exc : out std_logic; -- FP exception + cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes + cpo_ccv : out std_ulogic; -- FP condition codes valid + cpo_ldlock : out std_logic; -- FP pipeline hold + cpo_holdn : out std_ulogic; + cpo_dbg_data : out std_logic_vector(31 downto 0); + + rfi1_rd1addr : out std_logic_vector(3 downto 0); + rfi1_rd2addr : out std_logic_vector(3 downto 0); + rfi1_wraddr : out std_logic_vector(3 downto 0); + rfi1_wrdata : out std_logic_vector(31 downto 0); + rfi1_ren1 : out std_ulogic; + rfi1_ren2 : out std_ulogic; + rfi1_wren : out std_ulogic; + + rfi2_rd1addr : out std_logic_vector(3 downto 0); + rfi2_rd2addr : out std_logic_vector(3 downto 0); + rfi2_wraddr : out std_logic_vector(3 downto 0); + rfi2_wrdata : out std_logic_vector(31 downto 0); + rfi2_ren1 : out std_ulogic; + rfi2_ren2 : out std_ulogic; + rfi2_wren : out std_ulogic; + + rfo1_data1 : in std_logic_vector(31 downto 0); + rfo1_data2 : in std_logic_vector(31 downto 0); + rfo2_data1 : in std_logic_vector(31 downto 0); + rfo2_data2 : in std_logic_vector(31 downto 0) + ); + end component; + + component grfpw_net + generic (tech : integer := 0; + pclow : integer range 0 to 2 := 2; + dsu : integer range 0 to 2 := 1; + disas : integer range 0 to 2 := 0; + pipe : integer range 0 to 2 := 0 + ); + port ( + rst : in std_ulogic; -- Reset + clk : in std_ulogic; + holdn : in std_ulogic; -- pipeline hold + cpi_flush : in std_ulogic; -- pipeline flush + cpi_exack : in std_ulogic; -- FP exception acknowledge + cpi_a_rs1 : in std_logic_vector(4 downto 0); + cpi_d_pc : in std_logic_vector(31 downto 0); + cpi_d_inst : in std_logic_vector(31 downto 0); + cpi_d_cnt : in std_logic_vector(1 downto 0); + cpi_d_trap : in std_ulogic; + cpi_d_annul : in std_ulogic; + cpi_d_pv : in std_ulogic; + cpi_a_pc : in std_logic_vector(31 downto 0); + cpi_a_inst : in std_logic_vector(31 downto 0); + cpi_a_cnt : in std_logic_vector(1 downto 0); + cpi_a_trap : in std_ulogic; + cpi_a_annul : in std_ulogic; + cpi_a_pv : in std_ulogic; + cpi_e_pc : in std_logic_vector(31 downto 0); + cpi_e_inst : in std_logic_vector(31 downto 0); + cpi_e_cnt : in std_logic_vector(1 downto 0); + cpi_e_trap : in std_ulogic; + cpi_e_annul : in std_ulogic; + cpi_e_pv : in std_ulogic; + cpi_m_pc : in std_logic_vector(31 downto 0); + cpi_m_inst : in std_logic_vector(31 downto 0); + cpi_m_cnt : in std_logic_vector(1 downto 0); + cpi_m_trap : in std_ulogic; + cpi_m_annul : in std_ulogic; + cpi_m_pv : in std_ulogic; + cpi_x_pc : in std_logic_vector(31 downto 0); + cpi_x_inst : in std_logic_vector(31 downto 0); + cpi_x_cnt : in std_logic_vector(1 downto 0); + cpi_x_trap : in std_ulogic; + cpi_x_annul : in std_ulogic; + cpi_x_pv : in std_ulogic; + cpi_lddata : in std_logic_vector(31 downto 0); -- load data + cpi_dbg_enable : in std_ulogic; + cpi_dbg_write : in std_ulogic; + cpi_dbg_fsr : in std_ulogic; -- FSR access + cpi_dbg_addr : in std_logic_vector(4 downto 0); + cpi_dbg_data : in std_logic_vector(31 downto 0); + cpo_data : out std_logic_vector(31 downto 0); -- store data + cpo_exc : out std_logic; -- FP exception + cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes + cpo_ccv : out std_ulogic; -- FP condition codes valid + cpo_ldlock : out std_logic; -- FP pipeline hold + cpo_holdn : out std_ulogic; + cpo_dbg_data : out std_logic_vector(31 downto 0); + + rfi1_rd1addr : out std_logic_vector(3 downto 0); + rfi1_rd2addr : out std_logic_vector(3 downto 0); + rfi1_wraddr : out std_logic_vector(3 downto 0); + rfi1_wrdata : out std_logic_vector(31 downto 0); + rfi1_ren1 : out std_ulogic; + rfi1_ren2 : out std_ulogic; + rfi1_wren : out std_ulogic; + + rfi2_rd1addr : out std_logic_vector(3 downto 0); + rfi2_rd2addr : out std_logic_vector(3 downto 0); + rfi2_wraddr : out std_logic_vector(3 downto 0); + rfi2_wrdata : out std_logic_vector(31 downto 0); + rfi2_ren1 : out std_ulogic; + rfi2_ren2 : out std_ulogic; + rfi2_wren : out std_ulogic; + + rfo1_data1 : in std_logic_vector(31 downto 0); + rfo1_data2 : in std_logic_vector(31 downto 0); + rfo2_data1 : in std_logic_vector(31 downto 0); + rfo2_data2 : in std_logic_vector(31 downto 0) + ); + end component; + + component leon3ft_net + generic ( + hindex : integer := 0; + fabtech : integer range 0 to NTECH := DEFFABTECH; + memtech : integer range 0 to NTECH := DEFMEMTECH; + nwindows : integer range 2 to 32 := 8; + dsu : integer range 0 to 1 := 0; + fpu : integer range 0 to 31 := 0; + v8 : integer range 0 to 63 := 0; + cp : integer range 0 to 1 := 0; + mac : integer range 0 to 1 := 0; + pclow : integer range 0 to 2 := 2; + notag : integer range 0 to 1 := 0; + nwp : integer range 0 to 4 := 0; + icen : integer range 0 to 1 := 0; + irepl : integer range 0 to 2 := 2; + isets : integer range 1 to 4 := 1; + ilinesize : integer range 4 to 8 := 4; + isetsize : integer range 1 to 256 := 1; + isetlock : integer range 0 to 1 := 0; + dcen : integer range 0 to 1 := 0; + drepl : integer range 0 to 2 := 2; + dsets : integer range 1 to 4 := 1; + dlinesize : integer range 4 to 8 := 4; + dsetsize : integer range 1 to 256 := 1; + dsetlock : integer range 0 to 1 := 0; + dsnoop : integer range 0 to 6 := 0; + ilram : integer range 0 to 1 := 0; + ilramsize : integer range 1 to 512 := 1; + ilramstart : integer range 0 to 255 := 16#8e#; + dlram : integer range 0 to 1 := 0; + dlramsize : integer range 1 to 512 := 1; + dlramstart : integer range 0 to 255 := 16#8f#; + mmuen : integer range 0 to 1 := 0; + itlbnum : integer range 2 to 64 := 8; + dtlbnum : integer range 2 to 64 := 8; + tlb_type : integer range 0 to 3 := 1; + tlb_rep : integer range 0 to 1 := 0; + lddel : integer range 1 to 2 := 2; + disas : integer range 0 to 2 := 0; + tbuf : integer range 0 to 64 := 0; + pwd : integer range 0 to 2 := 2; -- power-down + svt : integer range 0 to 1 := 1; -- single vector trapping + rstaddr : integer := 0; + smp : integer range 0 to 15 := 0; -- support SMP systems + iuft : integer range 0 to 4 := 0; + fpft : integer range 0 to 4 := 0; + cmft : integer range 0 to 1 := 0; + cached : integer := 0; + scantest : integer := 0; + mmupgsz : integer range 0 to 5 := 0 + + ); + + port ( + clk : in std_ulogic; + gclk : in std_ulogic; + rstn : in std_ulogic; + ahbix : in ahb_mst_in_type; + ahbox : out ahb_mst_out_type; + ahbsix : in ahb_slv_in_type; + ahbso : in ahb_slv_out_vector; + irqi_irl: in std_logic_vector(3 downto 0); + irqi_rst: in std_ulogic; + irqi_run: in std_ulogic; + + irqo_intack: out std_ulogic; + irqo_irl: out std_logic_vector(3 downto 0); + irqo_pwd: out std_ulogic; + + dbgi_dsuen: in std_ulogic; -- DSU enable + dbgi_denable: in std_ulogic; -- diagnostic register access enable + dbgi_dbreak: in std_ulogic; -- debug break-in + dbgi_step: in std_ulogic; -- single step + dbgi_halt: in std_ulogic; -- halt processor + dbgi_reset: in std_ulogic; -- reset processor + dbgi_dwrite: in std_ulogic; -- read/write + dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address + dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data + dbgi_btrapa: in std_ulogic; -- break on IU trap + dbgi_btrape: in std_ulogic; -- break on IU trap + dbgi_berror: in std_ulogic; -- break on IU error mode + dbgi_bwatch: in std_ulogic; -- break on IU watchpoint + dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1) + dbgi_tenable: in std_ulogic; + dbgi_timer: in std_logic_vector(30 downto 0); + + dbgo_data: out std_logic_vector(31 downto 0); + dbgo_crdy: out std_ulogic; + dbgo_dsu: out std_ulogic; + dbgo_dsumode: out std_ulogic; + dbgo_error: out std_ulogic; + dbgo_halt: out std_ulogic; + dbgo_pwd: out std_ulogic; + dbgo_idle: out std_ulogic; + dbgo_ipend: out std_ulogic; + dbgo_icnt: out std_ulogic +); + + end component; + +component ftmctrl_net + generic ( + hindex : integer := 0; + pindex : integer := 0; + romaddr : integer := 16#000#; + rommask : integer := 16#E00#; + ioaddr : integer := 16#200#; + iomask : integer := 16#E00#; + ramaddr : integer := 16#400#; + rammask : integer := 16#C00#; + paddr : integer := 0; + pmask : integer := 16#fff#; + wprot : integer := 0; + invclk : integer := 0; + fast : integer := 0; + romasel : integer := 28; + sdrasel : integer := 29; + srbanks : integer := 4; + ram8 : integer := 0; + ram16 : integer := 0; + sden : integer := 0; + sepbus : integer := 0; + sdbits : integer := 32; + sdlsb : integer := 2; -- set to 12 for the GE-HPE board + oepol : integer := 0; + edac : integer := 0; + syncrst : integer := 0; + pageburst : integer := 0; + scantest : integer := 0; + writefb : integer := 0; + tech : integer := 0 + ); + port ( + rst: in Std_ULogic; + clk: in Std_ULogic; + ahbsi: in ahb_slv_in_type; + ahbso: out ahb_slv_out_type; + apbi: in apb_slv_in_type; + apbo: out apb_slv_out_type; + memi_data: in Std_Logic_Vector(31 downto 0); + memi_brdyn: in Std_Logic; + memi_bexcn: in Std_Logic; + memi_writen: in Std_Logic; + memi_wrn: in Std_Logic_Vector(3 downto 0); + memi_bwidth: in Std_Logic_Vector(1 downto 0); + memi_sd: in Std_Logic_Vector(63 downto 0); + memi_cb: in Std_Logic_Vector(15 downto 0); + memi_scb: in Std_Logic_Vector(15 downto 0); + memi_edac: in Std_Logic; + memo_address: out Std_Logic_Vector(31 downto 0); + memo_data: out Std_Logic_Vector(31 downto 0); + memo_sddata: out Std_Logic_Vector(63 downto 0); + memo_ramsn: out Std_Logic_Vector(7 downto 0); + memo_ramoen: out Std_Logic_Vector(7 downto 0); + memo_ramn: out Std_ULogic; + memo_romn: out Std_ULogic; + memo_mben: out Std_Logic_Vector(3 downto 0); + memo_iosn: out Std_Logic; + memo_romsn: out Std_Logic_Vector(7 downto 0); + memo_oen: out Std_Logic; + memo_writen: out Std_Logic; + memo_wrn: out Std_Logic_Vector(3 downto 0); + memo_bdrive: out Std_Logic_Vector(3 downto 0); + memo_vbdrive: out Std_Logic_Vector(31 downto 0); + memo_svbdrive: out Std_Logic_Vector(63 downto 0); + memo_read: out Std_Logic; + memo_sa: out Std_Logic_Vector(14 downto 0); + memo_cb: out Std_Logic_Vector(15 downto 0); + memo_scb: out Std_Logic_Vector(15 downto 0); + memo_vcdrive: out Std_Logic_Vector(15 downto 0); + memo_svcdrive: out Std_Logic_Vector(15 downto 0); + memo_ce: out Std_ULogic; + sdo_sdcke: out Std_Logic_Vector( 1 downto 0); + sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); + sdo_sdwen: out Std_ULogic; + sdo_rasn: out Std_ULogic; + sdo_casn: out Std_ULogic; + sdo_dqm: out Std_Logic_Vector( 7 downto 0); + wpo_wprothit: in Std_ULogic); + +end component; + +component ssrctrl_net + generic ( + tech: Integer := 0; + bus16: Integer := 1); + port ( + rst: in Std_Logic; + clk: in Std_Logic; + + n_ahbsi_hsel: in Std_Logic_Vector(0 to 15); + n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0); + n_ahbsi_hwrite: in Std_Logic; + n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0); + n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0); + n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0); + n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0); + n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0); + n_ahbsi_hready: in Std_Logic; + n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0); + n_ahbsi_hmastlock:in Std_Logic; + n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3); + n_ahbsi_hcache: in Std_Logic; + n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0); + + n_ahbso_hready: out Std_Logic; + n_ahbso_hresp: out Std_Logic_Vector(1 downto 0); + n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0); + n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0); + n_ahbso_hcache: out Std_Logic; + n_ahbso_hirq: out Std_Logic_Vector(31 downto 0); + + n_apbi_psel: in Std_Logic_Vector(0 to 15); + n_apbi_penable: in Std_Logic; + n_apbi_paddr: in Std_Logic_Vector(31 downto 0); + n_apbi_pwrite: in Std_Logic; + n_apbi_pwdata: in Std_Logic_Vector(31 downto 0); + n_apbi_pirq: in Std_Logic_Vector(31 downto 0); + + n_apbo_prdata: out Std_Logic_Vector(31 downto 0); + n_apbo_pirq: out Std_Logic_Vector(31 downto 0); + + n_sri_data: in Std_Logic_Vector(31 downto 0); + n_sri_brdyn: in Std_Logic; + n_sri_bexcn: in Std_Logic; + n_sri_writen: in Std_Logic; + n_sri_wrn: in Std_Logic_Vector(3 downto 0); + n_sri_bwidth: in Std_Logic_Vector(1 downto 0); + n_sri_sd: in Std_Logic_Vector(63 downto 0); + n_sri_cb: in Std_Logic_Vector(7 downto 0); + n_sri_scb: in Std_Logic_Vector(7 downto 0); + n_sri_edac: in Std_Logic; + + n_sro_address: out Std_Logic_Vector(31 downto 0); + n_sro_data: out Std_Logic_Vector(31 downto 0); + n_sro_sddata: out Std_Logic_Vector(63 downto 0); + n_sro_ramsn: out Std_Logic_Vector(7 downto 0); + n_sro_ramoen: out Std_Logic_Vector(7 downto 0); + n_sro_ramn: out Std_Logic; + n_sro_romn: out Std_Logic; + n_sro_mben: out Std_Logic_Vector(3 downto 0); + n_sro_iosn: out Std_Logic; + n_sro_romsn: out Std_Logic_Vector(7 downto 0); + n_sro_oen: out Std_Logic; + n_sro_writen: out Std_Logic; + n_sro_wrn: out Std_Logic_Vector(3 downto 0); + n_sro_bdrive: out Std_Logic_Vector(3 downto 0); + n_sro_vbdrive: out Std_Logic_Vector(31 downto 0); + n_sro_svbdrive: out Std_Logic_Vector(63 downto 0); + n_sro_read: out Std_Logic; + n_sro_sa: out Std_Logic_Vector(14 downto 0); + n_sro_cb: out Std_Logic_Vector(7 downto 0); + n_sro_scb: out Std_Logic_Vector(7 downto 0); + n_sro_vcdrive: out Std_Logic_Vector(7 downto 0); + n_sro_svcdrive: out Std_Logic_Vector(7 downto 0); + n_sro_ce: out Std_Logic); +end component; + +end; diff --git a/techmap/rtl/syncram_2p.vhd b/techmap/rtl/syncram_2p.vhd new file mode 100644 index 0000000..9fc47f9 --- /dev/null +++ b/techmap/rtl/syncram_2p.vhd @@ -0,0 +1,269 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2010, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: syncram_2p +-- File: syncram_2p.vhd +-- Author: Jiri Gaisler - Gaisler Research +-- Description: syncronous 2-port ram with tech selection +------------------------------------------------------------------------------ + +library ieee; +library techmap; +use ieee.std_logic_1164.all; +use techmap.gencomp.all; +use work.allmem.all; + +entity syncram_2p is + generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; + sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0); + port ( + rclk : in std_ulogic; + renable : in std_ulogic; + raddress : in std_logic_vector((abits -1) downto 0); + dataout : out std_logic_vector((dbits -1) downto 0); + wclk : in std_ulogic; + write : in std_ulogic; + waddress : in std_logic_vector((abits -1) downto 0); + datain : in std_logic_vector((dbits -1) downto 0); + testin : in std_logic_vector(3 downto 0) := "0000"); +end; + +architecture rtl of syncram_2p is + +constant nctrl : integer := abits*2 + 4; +type wrfst_type is record + raddr : std_logic_vector(abits-1 downto 0); + waddr : std_logic_vector(abits-1 downto 0); + datain : std_logic_vector((dbits -1) downto 0); + write : std_logic; + renable : std_logic; +end record; + +type wrfst_type2 is record + waddr : std_logic_vector(abits-1 downto 0); + datain : std_logic_vector((dbits -1) downto 0); + write : std_logic; +end record; + +signal vcc, gnd : std_ulogic; +signal vgnd : std_logic_vector(dbits-1 downto 0); +signal r : wrfst_type; +signal r2 : wrfst_type2; +signal dataoutx : std_logic_vector((dbits -1) downto 0); +signal databp, testdata : std_logic_vector((dbits -1) downto 0); +constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0); + +begin + + vcc <= '1'; gnd <= '0'; vgnd <= (others => '0'); + + no_wrfst : if wrfst = 0 generate + scanbp : if SCANTESTBP generate + comb : process (waddress, raddress, datain, renable, write, testin) + variable tmp : std_logic_vector((dbits -1) downto 0); + variable ctrlsigs : std_logic_vector((nctrl -1) downto 0); + begin + ctrlsigs := testin(1 downto 0) & write & renable & raddress & waddress; + tmp := datain; + for i in 0 to nctrl-1 loop + tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i); + end loop; + testdata <= tmp; + end process; + reg : process(rclk) begin + if rising_edge(rclk) then databp <= testdata; end if; + end process; + dmuxout : for i in 0 to dbits-1 generate + x0 : grmux2 generic map (tech) + port map (dataoutx(i), databp(i), testin(3), dataout(i)); + end generate; + end generate; + noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate; + end generate; + + wrfst_gen : if wrfst = 1 generate + comb : process(r, r2, dataoutx, testin) begin + if (SCANTESTBP and (testin(3) = '1')) or + (((r.write and r.renable) = '1') and (r.raddr = r.waddr)) then + dataout <= r.datain; + elsif ((sepclk = 1) and ((r2.write and r.renable) = '1') and (r.raddr = r2.waddr)) then + dataout <= r2.datain; + else dataout <= dataoutx; end if; + end process; + reg : process(rclk) begin + if rising_edge(rclk) then + r.raddr <= raddress; r.waddr <= waddress; + r.datain <= datain; r.write <= write; + r.renable <= renable; + end if; + end process; + reg2gen : if sepclk = 1 generate + reg2 : process(wclk) begin + if rising_edge(wclk) then + r2.waddr <= waddress; + r2.datain <= datain; r2.write <= write; + end if; + end process; + end generate; + noreg2gen : if sepclk = 0 generate + r2.waddr <= (others => '0'); + r2.datain <= (others => '0'); r2.write <= '0'; + end generate; + end generate; + + inf : if tech = inferred generate + x0 : generic_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, wclk, raddress, waddress, datain, write, dataoutx); + end generate; + + xcv : if tech = virtex generate + x0 : virtex_syncram_dp generic map (abits, dbits) + port map (wclk, waddress, datain, open, write, write, + rclk, raddress, vgnd, dataoutx, renable, gnd); + end generate; + + xc2v : if (is_unisim(tech) = 1) and (tech /= virtex)generate + x0 : unisim_syncram_2p generic map (abits, dbits, sepclk, wrfst) + port map (rclk, renable, raddress, dataoutx, wclk, + write, waddress, datain); + end generate; + + vir : if tech = memvirage generate + d39 : if dbits = 39 generate + x0 : virage_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain); + end generate; + d32 : if dbits <= 32 generate + x0 : virage_syncram_dp generic map (abits, dbits) + port map (wclk, waddress, datain, open, write, write, + rclk, raddress, vgnd, dataoutx, renable, gnd); + end generate; + end generate; + + atrh : if tech = atc18rha generate + x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain, testin); + end generate; + + axc : if (tech = axcel) or (tech = axdsp) generate + x0 : axcel_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + proa : if tech = proasic generate + x0 : proasic_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + proa3 : if tech = apa3 generate + x0 : proasic3_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + fus : if tech = actfus generate + x0 : fusion_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + ihp : if tech = ihp25 generate + x0 : generic_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, wclk, raddress, waddress, datain, write, dataoutx); + end generate; + +-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue + alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or + (tech = stratix3) or (tech = cyclone3) generate + x0 : altera_syncram_dp generic map (abits, dbits) + port map (rclk, raddress, vgnd, dataoutx, renable, gnd, + wclk, waddress, datain, open, write, write); + end generate; + + rh_lib18t0 : if tech = rhlib18t generate + x0 : rh_lib18t_syncram_2p generic map (abits, dbits, sepclk) + port map (rclk, renable, raddress, dataoutx, wclk, write, waddress, datain, testin); + end generate; + + lat : if tech = lattice generate + x0 : ec_syncram_dp generic map (abits, dbits) + port map (wclk, waddress, datain, open, write, write, + rclk, raddress, vgnd, dataoutx, renable, gnd); + end generate; + + ut025 : if tech = ut25 generate + x0 : ut025crh_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + arti : if tech = memartisan generate + x0 : artisan_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain); + end generate; + + cust1 : if tech = custom1 generate + x0 : custom1_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain); + end generate; + + ecl : if tech = eclipse generate + x0 : eclipse_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, waddress, datain, write); + end generate; + + vir90 : if tech = memvirage90 generate + x0 : virage90_syncram_dp generic map (abits, dbits) + port map (wclk, waddress, datain, open, write, write, + rclk, raddress, vgnd, dataoutx, renable, gnd); + end generate; + + nex : if tech = easic90 generate + x0 : nextreme_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain); + end generate; + + smic : if tech = smic013 generate + x0 : smic13_syncram_2p generic map (abits, dbits) + port map (rclk, renable, raddress, dataoutx, + wclk, write, waddress, datain); + end generate; + +-- pragma translate_off + noram : if has_2pram(tech) = 0 generate + x : process + begin + assert false report "synram_2p: technology " & tech_table(tech) & + " not supported" + severity failure; + wait; + end process; + end generate; +-- pragma translate_on + +end; + diff --git a/techmap/sim/Makefile b/techmap/sim/Makefile new file mode 100644 index 0000000..5f0fb71 --- /dev/null +++ b/techmap/sim/Makefile @@ -0,0 +1,33 @@ +library = techmap + +rtl_files = ../rtl/*.vhd \ + ../rtl/*.vhd + +rtl_tb_files = ../rtl_tb/*.vhd + +vhdlfiles = $(rtl_files) + + +all: compile + +compile: lib + vcom -2008 -work $(library) $(vhdlfiles) | ccze -A + +#simulate: +# export top=$(top); \ +# vsim -quiet -gui $(library).$(top) -do run.do + + +clean: + rm -f transcript + rm -f *.wlf + rm -f wlf* + rm -rf $(library) + + +# default patterns + +lib: $(library) + +$(library): + vlib $(library) diff --git a/techmap/sim/modelsim.ini b/techmap/sim/modelsim.ini new file mode 100644 index 0000000..7b253a0 --- /dev/null +++ b/techmap/sim/modelsim.ini @@ -0,0 +1,58 @@ +
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+grlib = ../../grlib/sim/grlib/
+gaisler = ../../gaisler/sim/gaisler/
+tools = ../../tools/sim/tools/
+zpu = ../../zpu/sim/zpu/
+rena3 = ../../rena3/sim/rena3/
+
+[vcom]
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+Show_source = 1
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+CheckSynthesis = 1
+
+[vsim]
+Resolution = ps
+UserTimeUnit = default
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+[lmc]
+
+[msg_system]
+
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