test application: LED running light

add working testbench
make ise stuff working

10 files changed, 935 insertions, 123 deletions

diff --git a/s3estarter/rtl/fpga_types.vhd b/s3estarter/rtl/fpga_types.vhd
index 6ea4c5a..bd72b55 100644
--- a/s3estarter/rtl/fpga_types.vhd
+++ b/s3estarter/rtl/fpga_types.vhd
@@ -6,22 +6,30 @@ use ieee.std_logic_1164.all;
 package types is
 
     type fpga_button_in_t is record
-        east  : std_ulogic;
-        north : std_ulogic;
-        south : std_ulogic;
-        west  : std_ulogic;
+        east   : std_ulogic;
+        north  : std_ulogic;
+        south  : std_ulogic;
+        west   : std_ulogic;
     end record fpga_button_in_t;
 
 
     type fpga_clk_in_t is record
-        clk50 : std_ulogic;
-        aux   : std_ulogic;
-        sma   : std_ulogic;
+        clk50  : std_ulogic;
+        aux    : std_ulogic;
+        sma    : std_ulogic;
     end record fpga_clk_in_t;
 
+
     type fpga_led_out_t is record
-        data  : std_ulogic_vector(7 downto 0);
+        data   : std_ulogic_vector(7 downto 0);
     end record fpga_led_out_t;
 
 
+    type fpga_rotary_sw_in_t is record
+        a      : std_ulogic;
+        b      : std_ulogic;
+        center : std_ulogic;
+    end record fpga_rotary_sw_in_t;
+
+
 end package types;
diff --git a/s3estarter/rtl/ibox.vhd b/s3estarter/rtl/ibox.vhd
new file mode 100644
index 0000000..fc397d4
--- /dev/null
+++ b/s3estarter/rtl/ibox.vhd
@@ -0,0 +1,98 @@
+-- ibox design
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library s3estarter;
+use s3estarter.types.all;
+
+
+
+entity ibox is
+    port (
+        clk             : in    std_ulogic;
+        reset           : in    std_ulogic;
+
+        fpga_button     : in    fpga_button_in_t;
+        fpga_led        : out   fpga_led_out_t; 
+        fpga_rotary_sw  : in    fpga_rotary_sw_in_t
+    );
+end entity ibox;
+
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+
+architecture rtl of ibox is
+    
+    function gen_counter_max return positive is
+        variable result : positive;
+    begin
+        result := 5_000_000; 
+        -- pragma translate_off
+        result := 10;
+        -- pragma translate_on
+        return result;
+    end function gen_counter_max;
+
+    constant counter_width : positive := integer( ieee.math_real.ceil( ieee.math_real.log2( real( gen_counter_max+1))));
+    constant counter_max   : unsigned(counter_width-1 downto 0) := to_unsigned( gen_counter_max, counter_width);
+                           
+                           
+    signal leds            : std_ulogic_vector(7 downto 0);
+    signal leds_en         : std_ulogic;
+                           
+    signal counter         : unsigned(counter_width-1 downto 0);
+
+    type reg_t is record
+        counter            : unsigned(counter_width-1 downto 0);
+        leds_en            : std_ulogic;
+        leds               : std_ulogic_vector(7 downto 0);
+    end record reg_t;
+    constant default_reg_c : reg_t := (
+        counter  => (others => '0'),
+        leds_en  => '0',
+        leds     => "00000001"
+    );
+
+    signal r, r_in         : reg_t;
+
+begin
+    
+    comb: process( r)
+        variable v : reg_t;
+    begin
+        v             := r;
+        fpga_led.data <= v.leds;
+
+        if v.leds_en = '1' then
+            v.leds    := v.leds( v.leds'high-1 downto 0) & v.leds( v.leds'high);
+        end if;
+
+       
+        v.leds_en     := '0'; 
+        v.counter     := v.counter + 1;
+
+        if v.counter = counter_max then
+            v.leds_en := '1';
+            v.counter := (others => '0');
+        end if;
+
+        r_in          <= v;
+    end process;
+
+    seq: process
+    begin
+        wait until rising_edge(clk);
+
+        r     <= r_in;
+
+        if reset = '1' then
+            r <= default_reg_c;
+        end if;
+    end process;
+    
+
+end architecture rtl;
diff --git a/s3estarter/rtl/obox.vhd b/s3estarter/rtl/obox.vhd
index 0d1f14f..b6c4fcd 100644
--- a/s3estarter/rtl/obox.vhd
+++ b/s3estarter/rtl/obox.vhd
@@ -1,6 +1,8 @@
 -----------------------------------------------------

---- SPARTAN-3E STARTER KIT BOARD

---- obox-design 

+-- SPARTAN-3E STARTER KIT BOARD

+--

+-- obox-design 

+-- contains drivers for board hardware (ddr-ram e.g.)

 -----------------------------------------------------

 

 library s3estarter;

@@ -93,16 +95,14 @@ entity obox is
 

 --      -- ==== Discrete LEDs (LED) ====

 --      -- These are shared connections with the FX2 connector

-        fpga_led        : out   fpga_led_out_t 

+        fpga_led        : out   fpga_led_out_t;

 

 --      -- ==== PS/2 Mouse/Keyboard Port (PS2) ====

 --      PS2_CLK         : inout std_ulogic;

 --      PS2_DATA        : inout std_ulogic;

 

 --      -- ==== Rotary Pushbutton Switch (ROT) ====

---      ROT_A           : inout std_ulogic;

---      ROT_B           : inout std_ulogic;

---      ROT_CENTER      : inout std_ulogic;

+        fpga_rotary_sw  : in    fpga_rotary_sw_in_t

 

 --      -- ==== RS-232 Serial Ports (RS232) ====

 --      RS232_DCE_RXD   : inout std_ulogic;

@@ -167,8 +167,57 @@ entity obox is
 end entity obox;

 

 

+

+library ieee;

+use ieee.std_logic_1164.all;

+

+

 architecture rtl of obox is

+    

+    component ibox is

+        port (

+            clk             : in    std_ulogic;

+            reset           : in    std_ulogic;

+

+            fpga_button     : in    fpga_button_in_t;

+            fpga_led        : out   fpga_led_out_t;

+            fpga_rotary_sw  : in    fpga_rotary_sw_in_t

+        );

+    end component ibox;

+

+

+    signal clk            : std_ulogic;

+    signal reset          : std_ulogic;

+    signal reset_async    : std_ulogic;

+

+    signal reset_shiftreg : std_ulogic_vector(3 downto 0) := (others => '1');

+

 begin

+   

+    -- select clk and reset source 

+    clk         <= fpga_clk.clk50;

+    reset_async <= fpga_rotary_sw.center; 

+

+

+    -- generate synchronous reset

+    reset_synchronizer : process

+    begin

+        wait until rising_edge( clk);

+        reset_shiftreg <= reset_shiftreg( reset_shiftreg'high-1 downto 0) & reset_async;

+    end process;

+

+    reset <= reset_shiftreg( reset_shiftreg'high);

+

+

+    ibox_i0: ibox

+        port map (

+            clk            => clk,            -- : in    std_ulogic;

+            reset          => reset,          -- : in    std_ulogic;

+            

+            fpga_button    => fpga_button,    -- : in    fpga_button_in_t;

+            fpga_led       => fpga_led,       -- : out   fpga_led_out_t 

+            fpga_rotary_sw => fpga_rotary_sw  -- : in    fpga_rotary_sw_in_t

+        );

 

 end architecture rtl;

 

diff --git a/s3estarter/rtl/top.vhd b/s3estarter/rtl/top.vhd
index 0ba9320..ed4e5ff 100644
--- a/s3estarter/rtl/top.vhd
+++ b/s3estarter/rtl/top.vhd
@@ -1,6 +1,7 @@
 -----------------------------------------------------

---- SPARTAN-3E STARTER KIT BOARD

---- top

+-- SPARTAN-3E STARTER KIT BOARD

+-- top

+-- contains buffers (iobuf, bufg, iobufds etc.)

 -----------------------------------------------------

 

 library ieee;

@@ -11,58 +12,58 @@ entity top is
     port (

         -- ==== Analog-to-Digital Converter (ADC) ====

         -- some connections shared with SPI Flash, DAC, ADC, and AMP

-        AD_CONV         : inout std_ulogic;

+        AD_CONV         : inout std_logic;

 

         -- ==== Programmable Gain Amplifier (AMP) ====

         -- some connections shared with SPI Flash, DAC, ADC, and AMP

-        AMP_CS          : inout std_ulogic;

-        AMP_DOUT        : inout std_ulogic;

-        AMP_SHDN        : inout std_ulogic;

+        AMP_CS          : inout std_logic;

+        AMP_DOUT        : inout std_logic;

+        AMP_SHDN        : inout std_logic;

 

         -- ==== Pushbuttons (BTN) ====

-        BTN_EAST        : inout std_ulogic;

-        BTN_NORTH       : inout std_ulogic;

-        BTN_SOUTH       : inout std_ulogic;

-        BTN_WEST        : inout std_ulogic;

+        BTN_EAST        : inout std_logic;

+        BTN_NORTH       : inout std_logic;

+        BTN_SOUTH       : inout std_logic;

+        BTN_WEST        : inout std_logic;

 

         -- ==== Clock inputs (CLK) ====

-        CLK_50MHZ       : in std_ulogic;

+        CLK_50MHZ       : in std_logic;

                       

-        CLK_AUX         : in std_ulogic;

-        CLK_SMA         : in std_ulogic;

+        CLK_AUX         : in std_logic;

+        CLK_SMA         : in std_logic;

 

         -- ==== Digital-to-Analog Converter (DAC) ====

         -- some connections shared with SPI Flash, DAC, ADC, and AMP

-        DAC_CLR         : inout std_ulogic;

-        DAC_CS          : inout std_ulogic;

+        DAC_CLR         : inout std_logic;

+        DAC_CS          : inout std_logic;

 

         -- ==== 1-Wire Secure EEPROM (DS)

-        DS_WIRE         : inout std_ulogic;

+        DS_WIRE         : inout std_logic;

 

         -- ==== Ethernet PHY (E) ====

-        E_COL           : inout std_ulogic;

-        E_CRS           : inout std_ulogic;

-        E_MDC           : inout std_ulogic;

-        E_MDIO          : inout std_ulogic;

-        E_RX_CLK        : inout std_ulogic;

-        E_RX_DV         : inout std_ulogic;

-        E_RXD           : inout std_ulogic_vector(4 downto 0);

-        E_TX_CLK        : inout std_ulogic;

-        E_TX_EN         : inout std_ulogic;

-        E_TXD           : inout std_ulogic_vector(4 downto 0);

+        E_COL           : inout std_logic;

+        E_CRS           : inout std_logic;

+        E_MDC           : inout std_logic;

+        E_MDIO          : inout std_logic;

+        E_RX_CLK        : inout std_logic;

+        E_RX_DV         : inout std_logic;

+        E_RXD           : inout std_logic_vector(4 downto 0);

+        E_TX_CLK        : inout std_logic;

+        E_TX_EN         : inout std_logic;

+        E_TXD           : inout std_logic_vector(4 downto 0);

 

         -- ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====

-        FPGA_M0         : inout std_ulogic;

-        FPGA_M1         : inout std_ulogic;

-        FPGA_M2         : inout std_ulogic;

-        FPGA_INIT_B     : inout std_ulogic;

-        FPGA_RDWR_B     : inout std_ulogic;

-        FPGA_HSWAP      : inout std_ulogic;

+        FPGA_M0         : inout std_logic;

+        FPGA_M1         : inout std_logic;

+        FPGA_M2         : inout std_logic;

+        FPGA_INIT_B     : inout std_logic;

+        FPGA_RDWR_B     : inout std_logic;

+        FPGA_HSWAP      : inout std_logic;

 

         -- ==== FX2 Connector (FX2) ====

-        FX2_CLKIN       : inout std_ulogic;

-        FX2_CLKIO       : inout std_ulogic;

-        FX2_CLKOUT      : inout std_ulogic;

+        FX2_CLKIN       : inout std_logic;

+        FX2_CLKIO       : inout std_logic;

+        FX2_CLKOUT      : inout std_logic;

 

         -- These four connections are shared with the J1 6-pin accessory header

         --FX2_IO          : inout std_ulogic_vector(4 downto 1);

@@ -76,7 +77,7 @@ entity top is
         -- The discrete LEDs are shared with the following 8 FX2 connections

         --FX2_IO        : inout std_ulogic_vector(20 downto 13);

         --FX2_IO          : inout std_ulogic_vector(40 downto 21);

-        FX2_IO          : inout std_ulogic_vector(40 downto 0);

+        FX2_IO          : inout std_logic_vector(40 downto 0);

 

         -- ==== 6-pin header J1 ====

         -- These are shared connections with the FX2 connector

@@ -91,85 +92,85 @@ entity top is
         --J4            : inout std_ulogic_vector(3 downto 0);

 

         -- ==== Character LCD (LCD) ====

-        LCD_E           : inout std_ulogic;

-        LCD_RS          : inout std_ulogic;

-        LCD_RW          : inout std_ulogic;

+        LCD_E           : inout std_logic;

+        LCD_RS          : inout std_logic;

+        LCD_RW          : inout std_logic;

 

         -- LCD data connections are shared with StrataFlash connections SF_D<11:8>

         --SF_D          : inout std_ulogic_vector(11 downto 8);

 

         -- ==== Discrete LEDs (LED) ====

         -- These are shared connections with the FX2 connector

-        LED             : inout std_ulogic_vector(7 downto 0);

+        LED             : inout std_logic_vector(7 downto 0);

 

         -- ==== PS/2 Mouse/Keyboard Port (PS2) ====

-        PS2_CLK         : inout std_ulogic;

-        PS2_DATA        : inout std_ulogic;

+        PS2_CLK         : inout std_logic;

+        PS2_DATA        : inout std_logic;

 

         -- ==== Rotary Pushbutton Switch (ROT) ====

-        ROT_A           : inout std_ulogic;

-        ROT_B           : inout std_ulogic;

-        ROT_CENTER      : inout std_ulogic;

+        ROT_A           : in    std_logic;

+        ROT_B           : in    std_logic;

+        ROT_CENTER      : in    std_logic;

 

         -- ==== RS-232 Serial Ports (RS232) ====

-        RS232_DCE_RXD   : inout std_ulogic;

-        RS232_DCE_TXD   : inout std_ulogic;

-        RS232_DTE_RXD   : inout std_ulogic;

-        RS232_DTE_TXD   : inout std_ulogic;

+        RS232_DCE_RXD   : inout std_logic;

+        RS232_DCE_TXD   : inout std_logic;

+        RS232_DTE_RXD   : inout std_logic;

+        RS232_DTE_TXD   : inout std_logic;

 

         -- ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)

-        SD_A            : inout std_ulogic_vector(12 downto 0);

-        SD_BA           : inout std_ulogic_vector(1 downto 0);

-        SD_CAS          : inout std_ulogic;

-        SD_CK_N         : inout std_ulogic;

-        SD_CK_P         : inout std_ulogic;

-        SD_CKE          : inout std_ulogic;

-        SD_CS           : inout std_ulogic;

-        SD_DQ           : inout std_ulogic_vector(15 downto 0);

-        SD_LDM          : inout std_ulogic;

-        SD_LDQS         : inout std_ulogic;

-        SD_RAS          : inout std_ulogic;

-        SD_UDM          : inout std_ulogic;

-        SD_UDQS         : inout std_ulogic;

-        SD_WE           : inout std_ulogic;

+        SD_A            : inout std_logic_vector(12 downto 0);

+        SD_BA           : inout std_logic_vector(1 downto 0);

+        SD_CAS          : inout std_logic;

+        SD_CK_N         : inout std_logic;

+        SD_CK_P         : inout std_logic;

+        SD_CKE          : inout std_logic;

+        SD_CS           : inout std_logic;

+        SD_DQ           : inout std_logic_vector(15 downto 0);

+        SD_LDM          : inout std_logic;

+        SD_LDQS         : inout std_logic;

+        SD_RAS          : inout std_logic;

+        SD_UDM          : inout std_logic;

+        SD_UDQS         : inout std_logic;

+        SD_WE           : inout std_logic;

 

         -- Path to allow connection to top DCM connection

-        SD_CK_FB        : inout std_ulogic;

+        SD_CK_FB        : inout std_logic;

 

         -- ==== Intel StrataFlash Parallel NOR Flash (SF) ====

-        SF_A            : inout std_ulogic_vector(24 downto 0);

-        SF_BYTE         : inout std_ulogic;

-        SF_CE0          : inout std_ulogic;

-        SF_D            : inout std_ulogic_vector(15 downto 1);

-        SF_OE           : inout std_ulogic;

-        SF_STS          : inout std_ulogic;

-        SF_WE           : inout std_ulogic;

+        SF_A            : inout std_logic_vector(24 downto 0);

+        SF_BYTE         : inout std_logic;

+        SF_CE0          : inout std_logic;

+        SF_D            : inout std_logic_vector(15 downto 1);

+        SF_OE           : inout std_logic;

+        SF_STS          : inout std_logic;

+        SF_WE           : inout std_logic;

 

         -- ==== STMicro SPI serial Flash (SPI) ====

         -- some connections shared with SPI Flash, DAC, ADC, and AMP

-        SPI_MISO        : inout std_ulogic;

-        SPI_MOSI        : inout std_ulogic;

-        SPI_SCK         : inout std_ulogic;

-        SPI_SS_B        : inout std_ulogic;

-        SPI_ALT_CS_JP11 : inout std_ulogic;

+        SPI_MISO        : inout std_logic;

+        SPI_MOSI        : inout std_logic;

+        SPI_SCK         : inout std_logic;

+        SPI_SS_B        : inout std_logic;

+        SPI_ALT_CS_JP11 : inout std_logic;

 

         -- ==== Slide Switches (SW) ====

-        SW              : inout std_ulogic_vector(3 downto 0);

+        SW              : inout std_logic_vector(3 downto 0);

 

         -- ==== VGA Port (VGA) ====

-        VGA_BLUE        : inout std_ulogic;

-        VGA_GREEN       : inout std_ulogic;

-        VGA_HSYNC       : inout std_ulogic;

-        VGA_RED         : inout std_ulogic;

-        VGA_VSYNC       : inout std_ulogic;

+        VGA_BLUE        : inout std_logic;

+        VGA_GREEN       : inout std_logic;

+        VGA_HSYNC       : inout std_logic;

+        VGA_RED         : inout std_logic;

+        VGA_VSYNC       : inout std_logic;

 

         -- ==== Xilinx CPLD (XC) ====

-        XC_CMD          : inout std_ulogic_vector(1 downto 0);

-        XC_CPLD_EN      : inout std_ulogic;

-        XC_D            : inout std_ulogic_vector(2 downto 0);

-        XC_TRIG         : inout std_ulogic;

-        XC_GCK0         : inout std_ulogic;

-        GCLK10          : inout std_ulogic

+        XC_CMD          : inout std_logic_vector(1 downto 0);

+        XC_CPLD_EN      : inout std_logic;

+        XC_D            : inout std_logic_vector(2 downto 0);

+        XC_TRIG         : inout std_logic;

+        XC_GCK0         : inout std_logic;

+        GCLK10          : inout std_logic

     );

 end entity top;

 

@@ -185,33 +186,40 @@ architecture rtl of top is
         port (

             fpga_button     : in    fpga_button_in_t;

             fpga_clk        : in    fpga_clk_in_t;

-            fpga_led        : out   fpga_led_out_t 

+            fpga_led        : out   fpga_led_out_t;

+            fpga_rotary_sw  : in    fpga_rotary_sw_in_t

         );

     end component obox;

 

     signal top_fpga_button     : fpga_button_in_t;

     signal top_fpga_clk        : fpga_clk_in_t;

+    signal top_fpga_rotary_sw  : fpga_rotary_sw_in_t;

     

     signal obox_i0_fpga_led    : fpga_led_out_t;

 

 begin

 

-    top_fpga_button.east  <= BTN_EAST;

-    top_fpga_button.north <= BTN_NORTH;

-    top_fpga_button.south <= BTN_SOUTH;

-    top_fpga_button.west  <= BTN_WEST;

+    top_fpga_button.east      <= BTN_EAST;

+    top_fpga_button.north     <= BTN_NORTH;

+    top_fpga_button.south     <= BTN_SOUTH;

+    top_fpga_button.west      <= BTN_WEST;

+                              

+    top_fpga_clk.clk50        <= CLK_50MHZ;

+    top_fpga_clk.aux          <= CLK_AUX;

+    top_fpga_clk.sma          <= CLK_SMA;

 

-    top_fpga_clk.clk50    <= CLK_50MHZ;

-    top_fpga_clk.aux      <= CLK_AUX;

-    top_fpga_clk.sma      <= CLK_SMA;

+    top_fpga_rotary_sw.a      <= ROT_A; 

+    top_fpga_rotary_sw.b      <= ROT_B;

+    top_fpga_rotary_sw.center <= ROT_CENTER;

 

     obox_i0: obox

         port map (

-            fpga_button => top_fpga_button,         -- : in    fpga_button_in_t;

-            fpga_clk    => top_fpga_clk,            -- : in    fpga_clk_in_t;

-            fpga_led    => obox_i0_fpga_led         -- : out   fpga_led_out_t 

+            fpga_button     => top_fpga_button,     -- : in    fpga_button_in_t;

+            fpga_clk        => top_fpga_clk,        -- : in    fpga_clk_in_t;

+            fpga_led        => obox_i0_fpga_led,    -- : out   fpga_led_out_t 

+            fpga_rotary_sw  => top_fpga_rotary_sw   -- : in    fpga_rotary_sw_in_t

         );

 

-    LED                   <= obox_i0_fpga_led.data;

+    LED                   <= std_logic_vector( obox_i0_fpga_led.data);

 

 end architecture rtl;

diff --git a/s3estarter/rtl_tb/top_tb.vhd b/s3estarter/rtl_tb/top_tb.vhd
new file mode 100644
index 0000000..1a16278
--- /dev/null
+++ b/s3estarter/rtl_tb/top_tb.vhd
@@ -0,0 +1,479 @@
+entity top_tb is
+end entity top_tb;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+architecture testbench of top_tb is
+    
+    
+    
+    component top is
+        port (
+            -- ==== Analog-to-Digital Converter (ADC) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+            AD_CONV         : inout std_logic;
+
+            -- ==== Programmable Gain Amplifier (AMP) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+            AMP_CS          : inout std_logic;
+            AMP_DOUT        : inout std_logic;
+            AMP_SHDN        : inout std_logic;
+
+            -- ==== Pushbuttons (BTN) ====
+            BTN_EAST        : inout std_logic;
+            BTN_NORTH       : inout std_logic;
+            BTN_SOUTH       : inout std_logic;
+            BTN_WEST        : inout std_logic;
+
+            -- ==== Clock inputs (CLK) ====
+            CLK_50MHZ       : in std_logic;
+                          
+            CLK_AUX         : in std_logic;
+            CLK_SMA         : in std_logic;
+
+            -- ==== Digital-to-Analog Converter (DAC) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+            DAC_CLR         : inout std_logic;
+            DAC_CS          : inout std_logic;
+
+            -- ==== 1-Wire Secure EEPROM (DS)
+            DS_WIRE         : inout std_logic;
+
+            -- ==== Ethernet PHY (E) ====
+            E_COL           : inout std_logic;
+            E_CRS           : inout std_logic;
+            E_MDC           : inout std_logic;
+            E_MDIO          : inout std_logic;
+            E_RX_CLK        : inout std_logic;
+            E_RX_DV         : inout std_logic;
+            E_RXD           : inout std_logic_vector(4 downto 0);
+            E_TX_CLK        : inout std_logic;
+            E_TX_EN         : inout std_logic;
+            E_TXD           : inout std_logic_vector(4 downto 0);
+
+            -- ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
+            FPGA_M0         : inout std_logic;
+            FPGA_M1         : inout std_logic;
+            FPGA_M2         : inout std_logic;
+            FPGA_INIT_B     : inout std_logic;
+            FPGA_RDWR_B     : inout std_logic;
+            FPGA_HSWAP      : inout std_logic;
+
+            -- ==== FX2 Connector (FX2) ====
+            FX2_CLKIN       : inout std_logic;
+            FX2_CLKIO       : inout std_logic;
+            FX2_CLKOUT      : inout std_logic;
+
+            -- These four connections are shared with the J1 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(4 downto 1);
+
+            -- These four connections are shared with the J2 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(8 downto 5);
+
+            -- These four connections are shared with the J4 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(12 downto 9);
+
+            -- The discrete LEDs are shared with the following 8 FX2 connections
+            --FX2_IO        : inout std_logic_vector(20 downto 13);
+            --FX2_IO          : inout std_logic_vector(40 downto 21);
+            FX2_IO          : inout std_logic_vector(40 downto 0);
+
+            -- ==== 6-pin header J1 ====
+            -- These are shared connections with the FX2 connector
+            --J1            : inout std_logic_vector(3 downto 0);
+
+            -- ==== 6-pin header J2 ====
+            -- These are shared connections with the FX2 connector
+            --J2            : inout std_logic_vector(3 downto 0);
+
+            -- ==== 6-pin header J4 ====
+            -- These are shared connections with the FX2 connector
+            --J4            : inout std_logic_vector(3 downto 0);
+
+            -- ==== Character LCD (LCD) ====
+            LCD_E           : inout std_logic;
+            LCD_RS          : inout std_logic;
+            LCD_RW          : inout std_logic;
+
+            -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+            --SF_D          : inout std_logic_vector(11 downto 8);
+
+            -- ==== Discrete LEDs (LED) ====
+            -- These are shared connections with the FX2 connector
+            LED             : inout std_logic_vector(7 downto 0);
+
+            -- ==== PS/2 Mouse/Keyboard Port (PS2) ====
+            PS2_CLK         : inout std_logic;
+            PS2_DATA        : inout std_logic;
+
+            -- ==== Rotary Pushbutton Switch (ROT) ====
+            ROT_A           : in    std_logic;
+            ROT_B           : in    std_logic;
+            ROT_CENTER      : in    std_logic;
+
+            -- ==== RS-232 Serial Ports (RS232) ====
+            RS232_DCE_RXD   : inout std_logic;
+            RS232_DCE_TXD   : inout std_logic;
+            RS232_DTE_RXD   : inout std_logic;
+            RS232_DTE_TXD   : inout std_logic;
+
+            -- ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
+            SD_A            : inout std_logic_vector(12 downto 0);
+            SD_BA           : inout std_logic_vector(1 downto 0);
+            SD_CAS          : inout std_logic;
+            SD_CK_N         : inout std_logic;
+            SD_CK_P         : inout std_logic;
+            SD_CKE          : inout std_logic;
+            SD_CS           : inout std_logic;
+            SD_DQ           : inout std_logic_vector(15 downto 0);
+            SD_LDM          : inout std_logic;
+            SD_LDQS         : inout std_logic;
+            SD_RAS          : inout std_logic;
+            SD_UDM          : inout std_logic;
+            SD_UDQS         : inout std_logic;
+            SD_WE           : inout std_logic;
+
+            -- Path to allow connection to top DCM connection
+            SD_CK_FB        : inout std_logic;
+
+            -- ==== Intel StrataFlash Parallel NOR Flash (SF) ====
+            SF_A            : inout std_logic_vector(24 downto 0);
+            SF_BYTE         : inout std_logic;
+            SF_CE0          : inout std_logic;
+            SF_D            : inout std_logic_vector(15 downto 1);
+            SF_OE           : inout std_logic;
+            SF_STS          : inout std_logic;
+            SF_WE           : inout std_logic;
+
+            -- ==== STMicro SPI serial Flash (SPI) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+            SPI_MISO        : inout std_logic;
+            SPI_MOSI        : inout std_logic;
+            SPI_SCK         : inout std_logic;
+            SPI_SS_B        : inout std_logic;
+            SPI_ALT_CS_JP11 : inout std_logic;
+
+            -- ==== Slide Switches (SW) ====
+            SW              : inout std_logic_vector(3 downto 0);
+
+            -- ==== VGA Port (VGA) ====
+            VGA_BLUE        : inout std_logic;
+            VGA_GREEN       : inout std_logic;
+            VGA_HSYNC       : inout std_logic;
+            VGA_RED         : inout std_logic;
+            VGA_VSYNC       : inout std_logic;
+
+            -- ==== Xilinx CPLD (XC) ====
+            XC_CMD          : inout std_logic_vector(1 downto 0);
+            XC_CPLD_EN      : inout std_logic;
+            XC_D            : inout std_logic_vector(2 downto 0);
+            XC_TRIG         : inout std_logic;
+            XC_GCK0         : inout std_logic;
+            GCLK10          : inout std_logic
+        );
+    end component top;
+
+
+    constant tb_clk_period     : time := (1 sec / 50_000_000);
+
+
+    signal   simulation_run    : boolean := true;
+
+
+            -- ==== Analog-to-Digital Converter (ADC) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+    signal  tb_AD_CONV         : std_logic;
+
+            -- ==== Programmable Gain Amplifier (AMP) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+    signal  tb_AMP_CS          : std_logic;
+    signal  tb_AMP_DOUT        : std_logic;
+    signal  tb_AMP_SHDN        : std_logic;
+
+            -- ==== Pushbuttons (BTN) ====
+    signal  tb_BTN_EAST        : std_logic;
+    signal  tb_BTN_NORTH       : std_logic;
+    signal  tb_BTN_SOUTH       : std_logic;
+    signal  tb_BTN_WEST        : std_logic;
+
+            -- ==== Clock inputs (CLK) ====
+    signal  tb_CLK_50MHZ       : std_logic := '0';
+                          
+    signal  tb_CLK_AUX         : std_logic := '0';
+    signal  tb_CLK_SMA         : std_logic := '0';
+
+            -- ==== Digital-to-Analog Converter (DAC) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+    signal  tb_DAC_CLR         : std_logic;
+    signal  tb_DAC_CS          : std_logic;
+
+            -- ==== 1-Wire Secure EEPROM (DS)
+    signal  tb_DS_WIRE         : std_logic;
+
+            -- ==== Ethernet PHY (E) ====
+    signal  tb_E_COL           : std_logic;
+    signal  tb_E_CRS           : std_logic;
+    signal  tb_E_MDC           : std_logic;
+    signal  tb_E_MDIO          : std_logic;
+    signal  tb_E_RX_CLK        : std_logic;
+    signal  tb_E_RX_DV         : std_logic;
+    signal  tb_E_RXD           : std_logic_vector(4 downto 0);
+    signal  tb_E_TX_CLK        : std_logic;
+    signal  tb_E_TX_EN         : std_logic;
+    signal  tb_E_TXD           : std_logic_vector(4 downto 0);
+
+            -- ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
+    signal  tb_FPGA_M0         : std_logic;
+    signal  tb_FPGA_M1         : std_logic;
+    signal  tb_FPGA_M2         : std_logic;
+    signal  tb_FPGA_INIT_B     : std_logic;
+    signal  tb_FPGA_RDWR_B     : std_logic;
+    signal  tb_FPGA_HSWAP      : std_logic;
+
+            -- ==== FX2 Connector (FX2) ====
+    signal  tb_FX2_CLKIN       : std_logic;
+    signal  tb_FX2_CLKIO       : std_logic;
+    signal  tb_FX2_CLKOUT      : std_logic;
+
+            -- These four connections are shared with the J1 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(4 downto 1);
+
+            -- These four connections are shared with the J2 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(8 downto 5);
+
+            -- These four connections are shared with the J4 6-pin accessory header
+            --FX2_IO          : inout std_logic_vector(12 downto 9);
+
+            -- The discrete LEDs are shared with the following 8 FX2 connections
+            --FX2_IO        : inout std_logic_vector(20 downto 13);
+            --FX2_IO          : inout std_logic_vector(40 downto 21);
+    signal  tb_FX2_IO          : std_logic_vector(40 downto 0);
+
+            -- ==== 6-pin header J1 ====
+            -- These are shared connections with the FX2 connector
+            --J1            : inout std_logic_vector(3 downto 0);
+
+            -- ==== 6-pin header J2 ====
+            -- These are shared connections with the FX2 connector
+            --J2            : inout std_logic_vector(3 downto 0);
+
+            -- ==== 6-pin header J4 ====
+            -- These are shared connections with the FX2 connector
+            --J4            : inout std_logic_vector(3 downto 0);
+
+            -- ==== Character LCD (LCD) ====
+    signal  tb_LCD_E           : std_logic;
+    signal  tb_LCD_RS          : std_logic;
+    signal  tb_LCD_RW          : std_logic;
+
+            -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+            --SF_D          : inout std_logic_vector(11 downto 8);
+
+            -- ==== Discrete LEDs (LED) ====
+            -- These are shared connections with the FX2 connector
+    signal  tb_LED             : std_logic_vector(7 downto 0);
+
+            -- ==== PS/2 Mouse/Keyboard Port (PS2) ====
+    signal  tb_PS2_CLK         : std_logic;
+    signal  tb_PS2_DATA        : std_logic;
+
+            -- ==== Rotary Pushbutton Switch (ROT) ====
+    signal  tb_ROT_A           : std_logic;
+    signal  tb_ROT_B           : std_logic;
+    signal  tb_ROT_CENTER      : std_logic;
+
+            -- ==== RS-232 Serial Ports (RS232) ====
+    signal  tb_RS232_DCE_RXD   : std_logic;
+    signal  tb_RS232_DCE_TXD   : std_logic;
+    signal  tb_RS232_DTE_RXD   : std_logic;
+    signal  tb_RS232_DTE_TXD   : std_logic;
+
+            -- ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
+    signal  tb_SD_A            : std_logic_vector(12 downto 0);
+    signal  tb_SD_BA           : std_logic_vector(1 downto 0);
+    signal  tb_SD_CAS          : std_logic;
+    signal  tb_SD_CK_N         : std_logic;
+    signal  tb_SD_CK_P         : std_logic;
+    signal  tb_SD_CKE          : std_logic;
+    signal  tb_SD_CS           : std_logic;
+    signal  tb_SD_DQ           : std_logic_vector(15 downto 0);
+    signal  tb_SD_LDM          : std_logic;
+    signal  tb_SD_LDQS         : std_logic;
+    signal  tb_SD_RAS          : std_logic;
+    signal  tb_SD_UDM          : std_logic;
+    signal  tb_SD_UDQS         : std_logic;
+    signal  tb_SD_WE           : std_logic;
+
+            -- Path to allow connection to top DCM connection
+    signal  tb_SD_CK_FB        : std_logic;
+
+            -- ==== Intel StrataFlash Parallel NOR Flash (SF) ====
+    signal  tb_SF_A            : std_logic_vector(24 downto 0);
+    signal  tb_SF_BYTE         : std_logic;
+    signal  tb_SF_CE0          : std_logic;
+    signal  tb_SF_D            : std_logic_vector(15 downto 1);
+    signal  tb_SF_OE           : std_logic;
+    signal  tb_SF_STS          : std_logic;
+    signal  tb_SF_WE           : std_logic;
+
+            -- ==== STMicro SPI serial Flash (SPI) ====
+            -- some connections shared with SPI Flash, DAC, ADC, and AMP
+    signal  tb_SPI_MISO        : std_logic;
+    signal  tb_SPI_MOSI        : std_logic;
+    signal  tb_SPI_SCK         : std_logic;
+    signal  tb_SPI_SS_B        : std_logic;
+    signal  tb_SPI_ALT_CS_JP11 : std_logic;
+
+            -- ==== Slide Switches (SW) ====
+    signal  tb_SW              : std_logic_vector(3 downto 0);
+
+            -- ==== VGA Port (VGA) ====
+    signal  tb_VGA_BLUE        : std_logic;
+    signal  tb_VGA_GREEN       : std_logic;
+    signal  tb_VGA_HSYNC       : std_logic;
+    signal  tb_VGA_RED         : std_logic;
+    signal  tb_VGA_VSYNC       : std_logic;
+
+            -- ==== Xilinx CPLD (XC) ====
+    signal  tb_XC_CMD          : std_logic_vector(1 downto 0);
+    signal  tb_XC_CPLD_EN      : std_logic;
+    signal  tb_XC_D            : std_logic_vector(2 downto 0);
+    signal  tb_XC_TRIG         : std_logic;
+    signal  tb_XC_GCK0         : std_logic;
+    signal  tb_GCLK10          : std_logic;
+
+
+
+
+begin
+
+    tb_CLK_50MHZ  <= not tb_CLK_50MHZ after tb_clk_period/2 when simulation_run;
+    tb_ROT_CENTER <= '1', '0' after 10 * tb_clk_period;
+
+    top_i0: top
+        port map (
+            AD_CONV         => tb_AD_CONV         , -- : inout std_ulogic;
+
+            AMP_CS          => tb_AMP_CS          , -- : inout std_ulogic;
+            AMP_DOUT        => tb_AMP_DOUT        , -- : inout std_ulogic;
+            AMP_SHDN        => tb_AMP_SHDN        , -- : inout std_ulogic;
+
+            BTN_EAST        => tb_BTN_EAST        , -- : inout std_ulogic;
+            BTN_NORTH       => tb_BTN_NORTH       , -- : inout std_ulogic;
+            BTN_SOUTH       => tb_BTN_SOUTH       , -- : inout std_ulogic;
+            BTN_WEST        => tb_BTN_WEST        , -- : inout std_ulogic;
+
+            CLK_50MHZ       => tb_CLK_50MHZ       , -- : in std_ulogic;
+
+            CLK_AUX         => tb_CLK_AUX         , -- : in std_ulogic;
+            CLK_SMA         => tb_CLK_SMA         , -- : in std_ulogic;
+
+            DAC_CLR         => tb_DAC_CLR         , -- : inout std_ulogic;
+            DAC_CS          => tb_DAC_CS          , -- : inout std_ulogic;
+
+            DS_WIRE         => tb_DS_WIRE         , -- : inout std_ulogic;
+
+            E_COL           => tb_E_COL           , -- : inout std_ulogic;
+            E_CRS           => tb_E_CRS           , -- : inout std_ulogic;
+            E_MDC           => tb_E_MDC           , -- : inout std_ulogic;
+            E_MDIO          => tb_E_MDIO          , -- : inout std_ulogic;
+            E_RX_CLK        => tb_E_RX_CLK        , -- : inout std_ulogic;
+            E_RX_DV         => tb_E_RX_DV         , -- : inout std_ulogic;
+            E_RXD           => tb_E_RXD           , -- : inout std_ulogic_vector(4 downto 0);
+            E_TX_CLK        => tb_E_TX_CLK        , -- : inout std_ulogic;
+            E_TX_EN         => tb_E_TX_EN         , -- : inout std_ulogic;
+            E_TXD           => tb_E_TXD           , -- : inout std_ulogic_vector(4 downto 0);
+
+            FPGA_M0         => tb_FPGA_M0         , -- : inout std_ulogic;
+            FPGA_M1         => tb_FPGA_M1         , -- : inout std_ulogic;
+            FPGA_M2         => tb_FPGA_M2         , -- : inout std_ulogic;
+            FPGA_INIT_B     => tb_FPGA_INIT_B     , -- : inout std_ulogic;
+            FPGA_RDWR_B     => tb_FPGA_RDWR_B     , -- : inout std_ulogic;
+            FPGA_HSWAP      => tb_FPGA_HSWAP      , -- : inout std_ulogic;
+
+            FX2_CLKIN       => tb_FX2_CLKIN       , -- : inout std_ulogic;
+            FX2_CLKIO       => tb_FX2_CLKIO       , -- : inout std_ulogic;
+            FX2_CLKOUT      => tb_FX2_CLKOUT      , -- : inout std_ulogic;
+
+            FX2_IO          => tb_FX2_IO          , -- : inout std_ulogic_vector(40 downto 0);
+
+            LCD_E           => tb_LCD_E           , -- : inout std_ulogic;
+            LCD_RS          => tb_LCD_RS          , -- : inout std_ulogic;
+            LCD_RW          => tb_LCD_RW          , -- : inout std_ulogic;
+
+            LED             => tb_LED             , -- : inout std_ulogic_vector(7 downto 0);
+
+            PS2_CLK         => tb_PS2_CLK         , -- : inout std_ulogic;
+            PS2_DATA        => tb_PS2_DATA        , -- : inout std_ulogic;
+
+            ROT_A           => tb_ROT_A           , -- : in    std_ulogic;
+            ROT_B           => tb_ROT_B           , -- : in    std_ulogic;
+            ROT_CENTER      => tb_ROT_CENTER      , -- : in    std_ulogic;
+
+            RS232_DCE_RXD   => tb_RS232_DCE_RXD   , -- : inout std_ulogic;
+            RS232_DCE_TXD   => tb_RS232_DCE_TXD   , -- : inout std_ulogic;
+            RS232_DTE_RXD   => tb_RS232_DTE_RXD   , -- : inout std_ulogic;
+            RS232_DTE_TXD   => tb_RS232_DTE_TXD   , -- : inout std_ulogic;
+
+            SD_A            => tb_SD_A            , -- : inout std_ulogic_vector(12 downto 0);
+            SD_BA           => tb_SD_BA           , -- : inout std_ulogic_vector(1 downto 0);
+            SD_CAS          => tb_SD_CAS          , -- : inout std_ulogic;
+            SD_CK_N         => tb_SD_CK_N         , -- : inout std_ulogic;
+            SD_CK_P         => tb_SD_CK_P         , -- : inout std_ulogic;
+            SD_CKE          => tb_SD_CKE          , -- : inout std_ulogic;
+            SD_CS           => tb_SD_CS           , -- : inout std_ulogic;
+            SD_DQ           => tb_SD_DQ           , -- : inout std_ulogic_vector(15 downto 0);
+            SD_LDM          => tb_SD_LDM          , -- : inout std_ulogic;
+            SD_LDQS         => tb_SD_LDQS         , -- : inout std_ulogic;
+            SD_RAS          => tb_SD_RAS          , -- : inout std_ulogic;
+            SD_UDM          => tb_SD_UDM          , -- : inout std_ulogic;
+            SD_UDQS         => tb_SD_UDQS         , -- : inout std_ulogic;
+            SD_WE           => tb_SD_WE           , -- : inout std_ulogic;
+
+            SD_CK_FB        => tb_SD_CK_FB        , -- : inout std_ulogic;
+
+            SF_A            => tb_SF_A            , -- : inout std_ulogic_vector(24 downto 0);
+            SF_BYTE         => tb_SF_BYTE         , -- : inout std_ulogic;
+            SF_CE0          => tb_SF_CE0          , -- : inout std_ulogic;
+            SF_D            => tb_SF_D            , -- : inout std_ulogic_vector(15 downto 1);
+            SF_OE           => tb_SF_OE           , -- : inout std_ulogic;
+            SF_STS          => tb_SF_STS          , -- : inout std_ulogic;
+            SF_WE           => tb_SF_WE           , -- : inout std_ulogic;
+
+            SPI_MISO        => tb_SPI_MISO        , -- : inout std_ulogic;
+            SPI_MOSI        => tb_SPI_MOSI        , -- : inout std_ulogic;
+            SPI_SCK         => tb_SPI_SCK         , -- : inout std_ulogic;
+            SPI_SS_B        => tb_SPI_SS_B        , -- : inout std_ulogic;
+            SPI_ALT_CS_JP11 => tb_SPI_ALT_CS_JP11 , -- : inout std_ulogic;
+
+            SW              => tb_SW              , -- : inout std_ulogic_vector(3 downto 0);
+
+            VGA_BLUE        => tb_VGA_BLUE        , -- : inout std_ulogic;
+            VGA_GREEN       => tb_VGA_GREEN       , -- : inout std_ulogic;
+            VGA_HSYNC       => tb_VGA_HSYNC       , -- : inout std_ulogic;
+            VGA_RED         => tb_VGA_RED         , -- : inout std_ulogic;
+            VGA_VSYNC       => tb_VGA_VSYNC       , -- : inout std_ulogic;
+
+            XC_CMD          => tb_XC_CMD          , -- : inout std_ulogic_vector(1 downto 0);
+            XC_CPLD_EN      => tb_XC_CPLD_EN      , -- : inout std_ulogic;
+            XC_D            => tb_XC_D            , -- : inout std_ulogic_vector(2 downto 0);
+            XC_TRIG         => tb_XC_TRIG         , -- : inout std_ulogic;
+            XC_GCK0         => tb_XC_GCK0         , -- : inout std_ulogic;
+            GCLK10          => tb_GCLK10            -- : inout std_ulogic
+        );
+
+
+    main: process
+    begin
+        report "bitwidth for counter to 15 : " & integer'image( integer( ieee.math_real.ceil( ieee.math_real.log2( real( 15 +1)))));
+        report "bitwidth for counter to 16 : " & integer'image( integer( ieee.math_real.ceil( ieee.math_real.log2( real( 16 +1)))));
+        wait for 50 us;
+        simulation_run <= false;
+        wait;
+    end process;
+
+end architecture testbench;
diff --git a/s3estarter/sim/Makefile b/s3estarter/sim/Makefile
index 0fdad54..59e450a 100755
--- a/s3estarter/sim/Makefile
+++ b/s3estarter/sim/Makefile
@@ -1,12 +1,12 @@
 library      = s3estarter
-top          = top
+top          = top_tb
 
 rtl_files    = ../rtl/fpga_types.vhd \
                ../rtl/*.vhd
 
 rtl_tb_files = ../rtl_tb/*.vhd
 
-vhdlfiles    = $(rtl_files) 
+vhdlfiles    = $(rtl_files) $(rtl_tb_files)
 
 
 all: compile simulate
diff --git a/s3estarter/sim/run.do b/s3estarter/sim/run.do
new file mode 100644
index 0000000..100b521
--- /dev/null
+++ b/s3estarter/sim/run.do
@@ -0,0 +1,57 @@
+

+#

+# helper functions

+#

+

+

+# neues Spiel, neues Glueck

+proc nsng {} {

+

+    restart -f

+    set StdArithNoWarnings 1

+    set NumericStdNoWarnings  1

+

+    when -label enable_Warn {reset == '0'} {echo "Enable Warnings" ; set StdArithNoWarnings 0 ; set NumericStdNoWarnings 0 ;}

+

+    run -all

+}

+

+

+proc r {} {

+    restart -f

+    run -all

+}

+

+

+proc my_debug {} {

+    global env

+    foreach key [array names env] {

+        puts "$key=$env($key)"

+    }

+}

+

+

+proc e {} {

+    exit -force

+}

+

+proc x {} {

+    exit -force

+}

+

+

+

+

+# get env variables

+global env

+quietly set top $env(top)

+

+

+if {[file exists wave_$top.do]} {

+    do wave_$top.do

+} else {

+    puts "INFO: no wave file (wave_$top.do) found"

+}

+

+

+run -all

diff --git a/s3estarter/sim/wave_top_tb.do b/s3estarter/sim/wave_top_tb.do
new file mode 100644
index 0000000..c9d7749
--- /dev/null
+++ b/s3estarter/sim/wave_top_tb.do
@@ -0,0 +1,29 @@
+onerror {resume}

+quietly WaveActivateNextPane {} 0

+add wave -noupdate -divider testbench

+add wave -noupdate -format Logic /top_tb/simulation_run

+add wave -noupdate -format Logic /top_tb/tb_clk_50mhz

+add wave -noupdate -format Logic /top_tb/tb_rot_center

+add wave -noupdate -divider ibox

+add wave -noupdate -format Logic /top_tb/top_i0/obox_i0/ibox_i0/reset

+add wave -noupdate -format Logic /top_tb/top_i0/obox_i0/ibox_i0/clk

+add wave -noupdate -format Literal -expand /top_tb/top_i0/obox_i0/ibox_i0/r

+add wave -noupdate -divider LEDs

+add wave -noupdate -format Literal /top_tb/tb_led

+TreeUpdate [SetDefaultTree]

+WaveRestoreCursors {{Cursor 1} {950000 ps} 0} {{Cursor 2} {510000 ps} 0}

+configure wave -namecolwidth 161

+configure wave -valuecolwidth 100

+configure wave -justifyvalue left

+configure wave -signalnamewidth 2

+configure wave -snapdistance 10

+configure wave -datasetprefix 0

+configure wave -rowmargin 4

+configure wave -childrowmargin 2

+configure wave -gridoffset 0

+configure wave -gridperiod 1

+configure wave -griddelta 40

+configure wave -timeline 0

+configure wave -timelineunits ps

+update

+WaveRestoreZoom {0 ps} {535500 ps}

diff --git a/s3estarter/syn/s3estarter.ucf b/s3estarter/syn/s3estarter.ucf
index 9cacd69..4fbe428 100755
--- a/s3estarter/syn/s3estarter.ucf
+++ b/s3estarter/syn/s3estarter.ucf
@@ -105,15 +105,15 @@ NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

-NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

 

 # ==== 6-pin header J1 ====

 # These are shared connections with the FX2 connector

@@ -304,5 +304,5 @@ NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
 NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

 NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;

 NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

-NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

 

diff --git a/s3estarter/syn/xst.xise b/s3estarter/syn/xst.xise
new file mode 100644
index 0000000..272656e
--- /dev/null
+++ b/s3estarter/syn/xst.xise
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="s3estarter.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../rtl/fpga_types.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <library xil_pn:name="s3estarter"/>
+    </file>
+    <file xil_pn:name="../rtl/ibox.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <library xil_pn:name="s3estarter"/>
+    </file>
+    <file xil_pn:name="../rtl/obox.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <library xil_pn:name="s3estarter"/>
+    </file>
+    <file xil_pn:name="../rtl/top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <library xil_pn:name="s3estarter"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../rtl/top.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-XE VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="xst" xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="xst" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-07-28T13:31:47" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CDB67F517F174923B9BFA7F953ADF4F5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries>
+    <library xil_pn:name="s3estarter"/>
+  </libraries>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>