change: try to switch to vmake generated makefiles

1 files changed, 15 insertions, 8 deletions

diff --git a/s3estarter/sim/Makefile b/s3estarter/sim/Makefile
index e189cc5..c0c59a2 100644
--- a/s3estarter/sim/Makefile
+++ b/s3estarter/sim/Makefile
@@ -14,15 +14,22 @@ vhdlfiles    = $(rtl_files) $(rtl_tb_files)
 
 all: compile simulate
 
+remake: lib Makefile.$(library)
+
+Makefile.$(library): $(vhdlfiles) $(library)
+	vcom -quiet -2008 -work $(library) $(vhdlfiles)
+	vmake $(library) > Makefile.$(library)
+	# patch winpath -> cygpath
+	sed -e 's/\(C:.*\)/$$(shell cygpath --unix "\1" | sed "s\/ \/\\\\\\\\ \/g" )/g' -i Makefile.$(library)
+
+
+compile:
+	make -f Makefile.$(library)
+
 compile_others:
-	#make --directory ../software/test/ test
-	make --directory ../software/ethernet_speed
-	make compile --directory ../../rena3/sim
-
-compile: lib
-	#vlog -work verilog "c:/Program_Files_BLa/Xilinx/12.2/ISE_DS/ISE/verilog/src/glbl.v"
-	#vlog -work verilog +incdir+../rtl_tb/ +define+sg6 +define+x16 $(verilogfiles)
-	vcom -2008 -work $(library) $(vhdlfiles) | ccze -A
+	make --directory ../software/test/ test | ccze -A
+	make compile --directory ../../zpu/sim | ccze -A
+	#make --directory ../software/ethernet_speed
 
 simulate:
 	export top=$(top); \