change: switch to vhdl 2008 syntax

3 files changed, 58 insertions, 55 deletions

diff --git a/gaisler/rtl_tb/sim.vhd b/gaisler/rtl_tb/sim.vhd
index 9aa02de..f52c04b 100644
--- a/gaisler/rtl_tb/sim.vhd
+++ b/gaisler/rtl_tb/sim.vhd
@@ -81,7 +81,7 @@ package sim is
   end component;  
 
   procedure hexread(L : inout line; value:out bit_vector);
-  procedure hexread(L : inout line; value:out std_logic_vector);
+  procedure hexread(L : inout line; value:out std_ulogic_vector);
   function ishex(c : character) return boolean;
   function buskeep(signal v : in std_logic_vector) return std_logic_vector;
   function buskeep(signal c : in std_logic) return std_logic;
@@ -431,12 +431,13 @@ package body sim is
     value := TO_X01(tmp);
   end hexread;
 
-  procedure hexread(L:inout line; value:out std_logic_vector) is
-    variable tmp: std_ulogic_vector(value'length-1 downto 0);	--'
-  begin
-    hexread(L, tmp);
-    value := std_logic_vector(tmp);
-  end hexread;
+-- VHDL 2008: slv is subtype of sulv
+--procedure hexread(L:inout line; value:out std_logic_vector) is
+--  variable tmp: std_ulogic_vector(value'length-1 downto 0);	--'
+--begin
+--  hexread(L, tmp);
+--  value := std_logic_vector(tmp);
+--end hexread;
 
   function ishex(c:character) return boolean is
   variable tmp : bit_vector(3 downto 0);
diff --git a/grlib/rtl_tb/stdio.vhd b/grlib/rtl_tb/stdio.vhd
index bc838db..83289c5 100644
--- a/grlib/rtl_tb/stdio.vhd
+++ b/grlib/rtl_tb/stdio.vhd
@@ -35,6 +35,7 @@ use      IEEE.Std_Logic_1164.all;
 package StdIO is
 
 -- pragma translate_off
+
    procedure HRead(
       variable L:          inout Line;
       variable VALUE:      out   Std_ULogic_Vector;
@@ -44,14 +45,15 @@ package StdIO is
       variable L:          inout Line;
       variable VALUE:      out   Std_ULogic_Vector);
 
-   procedure HRead(
-      variable L:          inout Line;
-      variable VALUE:      out   Std_Logic_Vector;
-      variable GOOD:       out   Boolean);
+-- VHDL 2008: slv is subtype from sulv
+-- procedure HRead(
+--    variable L:          inout Line;
+--    variable VALUE:      out   Std_Logic_Vector;
+--    variable GOOD:       out   Boolean);
 
-   procedure HRead(
-      variable L:          inout Line;
-      variable VALUE:      out   Std_Logic_Vector);
+-- procedure HRead(
+--    variable L:          inout Line;
+--    variable VALUE:      out   Std_Logic_Vector);
 
    procedure HWrite(
       variable L:          inout Line;
@@ -59,11 +61,11 @@ package StdIO is
       constant JUSTIFIED:  in    SIDE  := RIGHT;
       constant FIELD:      in    WIDTH := 0);
 
-   procedure HWrite(
-      variable L:          inout Line;
-      constant VALUE:      in    Std_Logic_Vector;
-      constant JUSTIFIED:  in    SIDE  := RIGHT;
-      constant FIELD:      in    WIDTH := 0);
+-- procedure HWrite(
+--    variable L:          inout Line;
+--    constant VALUE:      in    Std_Logic_Vector;
+--    constant JUSTIFIED:  in    SIDE  := RIGHT;
+--    constant FIELD:      in    WIDTH := 0);
 
    procedure Write(
       variable L:          inout Line;
@@ -195,27 +197,27 @@ package body StdIO is
          report "HREAD: access incorrect";
    end HRead;
 
-   procedure HRead(
-      variable L:          inout Line;
-      variable VALUE:      out   Std_Logic_Vector;
-      variable GOOD:       out   Boolean) is
-      variable V:                Std_ULogic_Vector(0 to Value'Length-1);
-   begin
-      HRead(L, V, GOOD);
-      VALUE := Std_Logic_Vector(V);
-   end HRead;
+-- procedure HRead(
+--    variable L:          inout Line;
+--    variable VALUE:      out   Std_Logic_Vector;
+--    variable GOOD:       out   Boolean) is
+--    variable V:                Std_ULogic_Vector(0 to Value'Length-1);
+-- begin
+--    HRead(L, V, GOOD);
+--    VALUE := Std_Logic_Vector(V);
+-- end HRead;
 
-   procedure HRead(
-      variable L:          inout Line;
-      variable VALUE:      out   Std_Logic_Vector) is
-      variable GOOD:             Boolean;
-      variable V:                Std_ULogic_Vector(0 to Value'Length-1);
-   begin
-      HRead(L, V, GOOD);
-      VALUE := Std_Logic_Vector(V);
-      assert GOOD
-         report "HREAD: access incorrect";
-   end HRead;
+-- procedure HRead(
+--    variable L:          inout Line;
+--    variable VALUE:      out   Std_Logic_Vector) is
+--    variable GOOD:             Boolean;
+--    variable V:                Std_ULogic_Vector(0 to Value'Length-1);
+-- begin
+--    HRead(L, V, GOOD);
+--    VALUE := Std_Logic_Vector(V);
+--    assert GOOD
+--       report "HREAD: access incorrect";
+-- end HRead;
 
    procedure HWrite(
       variable L:          inout Line;
@@ -242,14 +244,14 @@ package body StdIO is
       end if;
    end HWrite;
 
-   procedure HWrite(
-      variable L:          inout Line;
-      constant VALUE:      in    Std_Logic_Vector;
-      constant JUSTIFIED:  in    SIDE  := RIGHT;
-      constant FIELD:      in    WIDTH := 0) is
-   begin
-      HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
-   end HWrite;
+-- procedure HWrite(
+--    variable L:          inout Line;
+--    constant VALUE:      in    Std_Logic_Vector;
+--    constant JUSTIFIED:  in    SIDE  := RIGHT;
+--    constant FIELD:      in    WIDTH := 0) is
+-- begin
+--    HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
+-- end HWrite;
 
    procedure Write(
       variable L:          inout Line;
diff --git a/zpu/rtl_tb/txt_util.vhd b/zpu/rtl_tb/txt_util.vhd
index a863f65..c127b24 100644
--- a/zpu/rtl_tb/txt_util.vhd
+++ b/zpu/rtl_tb/txt_util.vhd
@@ -70,7 +70,7 @@ package txt_util is
     function str(int: integer) return string;

 

     -- convert std_logic_vector into a string in hex format

-    function hstr(slv: std_logic_vector) return string;

+--  function hstr(slv: std_logic_vector) return string;

     function hstr(slv: std_ulogic_vector) return string;

 

 

@@ -313,11 +313,11 @@ package body txt_util is
 

 

    -- converts a std_logic_vector into a hex string.

-   function hstr(slv: std_logic_vector) return string is

+   function hstr(slv: std_ulogic_vector) return string is

        variable hexlen: integer;

-       variable longslv : std_logic_vector(67 downto 0) := (others => '0');

+       variable longslv : std_ulogic_vector(67 downto 0) := (others => '0');

        variable hex : string(1 to 16);

-       variable fourbit : std_logic_vector(3 downto 0);

+       variable fourbit : std_ulogic_vector(3 downto 0);

      begin

        hexlen := (slv'left+1)/4;

        if (slv'left+1) mod 4 /= 0 then

@@ -352,10 +352,10 @@ package body txt_util is
        return hex(1 to hexlen);

      end hstr;

    

-   function hstr(slv: std_ulogic_vector) return string is

-   begin

-     return( hstr( std_logic_vector( slv)));

-   end hstr;

+-- function hstr(slv: std_ulogic_vector) return string is

+-- begin

+--   return( hstr( std_logic_vector( slv)));

+-- end hstr;