blob: 8824236e303fe815fe99a24008ba4a7b125fb1a5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
/*
* mcfmmu.h -- definitions for the ColdFire v4e MMU
*
* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef MCFMMU_H
#define MCFMMU_H
/*
* The MMU support registers are mapped into the address space using
* the processor MMUBASE register. We used a fixed address for mapping,
* there doesn't seem any need to make this configurable yet.
*/
#define MMUBASE 0xfe000000
/*
* The support registers of the MMU. Names are the sames as those
* used in the Freescale v4e documentation.
*/
#define MMUCR (MMUBASE + 0x00) /* Control register */
#define MMUOR (MMUBASE + 0x04) /* Operation register */
#define MMUSR (MMUBASE + 0x08) /* Status register */
#define MMUAR (MMUBASE + 0x10) /* TLB Address register */
#define MMUTR (MMUBASE + 0x14) /* TLB Tag register */
#define MMUDR (MMUBASE + 0x18) /* TLB Data register */
/*
* MMU Control register bit flags
*/
#define MMUCR_EN 0x00000001 /* Virtual mode enable */
#define MMUCR_ASM 0x00000002 /* Address space mode */
/*
* MMU Operation register.
*/
#define MMUOR_UAA 0x00000001 /* Update allocation address */
#define MMUOR_ACC 0x00000002 /* TLB access */
#define MMUOR_RD 0x00000004 /* TLB access read */
#define MMUOR_WR 0x00000000 /* TLB access write */
#define MMUOR_ADR 0x00000008 /* TLB address select */
#define MMUOR_ITLB 0x00000010 /* ITLB operation */
#define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
#define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
#define MMUOR_CA 0x00000080 /* Clear all TLBs */
#define MMUOR_STLB 0x00000100 /* Search TLBs */
#define MMUOR_AAN 16 /* TLB allocation address */
#define MMUOR_AAMASK 0xffff0000 /* AA mask */
/*
* MMU Status register.
*/
#define MMUSR_HIT 0x00000002 /* Search TLB hit */
#define MMUSR_WF 0x00000008 /* Write access fault */
#define MMUSR_RF 0x00000010 /* Read access fault */
#define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
/*
* MMU Read/Write Tag register.
*/
#define MMUTR_V 0x00000001 /* Valid */
#define MMUTR_SG 0x00000002 /* Shared global */
#define MMUTR_IDN 2 /* Address Space ID */
#define MMUTR_IDMASK 0x000003fc /* ASID mask */
#define MMUTR_VAN 10 /* Virtual Address */
#define MMUTR_VAMASK 0xfffffc00 /* VA mask */
/*
* MMU Read/Write Data register.
*/
#define MMUDR_LK 0x00000002 /* Lock entry */
#define MMUDR_X 0x00000004 /* Execute access enable */
#define MMUDR_W 0x00000008 /* Write access enable */
#define MMUDR_R 0x00000010 /* Read access enable */
#define MMUDR_SP 0x00000020 /* Supervisor access enable */
#define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */
#define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */
#define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
#define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
#define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */
#define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */
#define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */
#define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */
#define MMUDR_PAN 10 /* Physical address */
#define MMUDR_PAMASK 0xfffffc00 /* PA mask */
#ifndef __ASSEMBLY__
/*
* Simple access functions for the MMU registers. Nothing fancy
* currently required, just simple 32bit access.
*/
static inline u32 mmu_read(u32 a)
{
return *((volatile u32 *) a);
}
static inline void mmu_write(u32 a, u32 v)
{
*((volatile u32 *) a) = v;
__asm__ __volatile__ ("nop");
}
int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
#endif
#endif /* MCFMMU_H */
|
