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path: root/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
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* drm/nouveau/fifo: implement nvif event sourceBen Skeggs2014-08-101-14/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: allow direct access to channel control registers where ↵Ben Skeggs2014-08-101-0/+1
| | | | | | | | | | | | | | | possible The indirect method has been left in-place here as a fallback path, as it may not be possible to map the non-PAGE_SIZE aligned control areas across some chipset+interface combinations. This isn't a problem for the primary use-case where the core and drm are linked together in kernel-land, but across a VM or (in the case where it applies now) between the core in the kernel and a userspace test tool. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: audit and version fifo channel classesBen Skeggs2014-08-101-12/+23
| | | | | | | | The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: rework event interfaceBen Skeggs2014-08-101-10/+29
| | | | | | | | | | | | | | | This is a lot of prep-work for being able to send event notifications back to userspace. Events now contain data, rather than a "something just happened" signal. Handler data is now embedded into a containing structure, rather than being kmalloc()'d, and can optionally have the notify routine handled in a workqueue. Various races between suspend/unload with display HPD/DP IRQ handlers automagically solved as a result. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: allow event source to handle multiple event types per indexBen Skeggs2014-06-111-3/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: bind intrBen Skeggs2014-03-261-2/+27
| | | | | | Error code names from Android GK20A driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: attempt to recover from engine ctxsw timeoutsBen Skeggs2014-03-261-0/+44
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: attempt to recover engines from mmu faultsBen Skeggs2014-03-261-2/+87
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: allow copy engine channel to be looked up by instanceBen Skeggs2014-03-261-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: use runlist event instead of pollingBen Skeggs2014-03-261-1/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: allow channels to be marked as unrunnableBen Skeggs2014-03-261-13/+24
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: single printk for sched error dataBen Skeggs2014-03-261-4/+10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: single printk for mmu fault dataBen Skeggs2014-03-261-72/+92
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: ack pb intr individually after handling each unitBen Skeggs2014-03-261-66/+63
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: runlist intrBen Skeggs2014-03-261-10/+17
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: engine intrBen Skeggs2014-03-261-1/+7
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrsBen Skeggs2014-03-261-2/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: allocate usermem as neededAlexandre Courbot2014-03-261-2/+2
| | | | | | | | | Memory was always allocated for 4096 channels. Change this to allocate what we actually need according to the number of channels we use. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: fix ENG_RUNLIST register addressAlexandre Courbot2014-02-181-1/+1
| | | | | | | | Address of the ENG_RUNLIST register should be 0x002284 + (engine * 8), not 0x002284 + (engine * 4). Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bar: tidy up the subdev and object class definitionsBen Skeggs2014-01-231-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs2014-01-231-11/+20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs2014-01-231-1/+16
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs2014-01-231-11/+87
| | | | | | Ordering from Android GK20A driver, names from binary driver strings. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: document more intr status bitsBen Skeggs2014-01-231-5/+72
| | | | | | As per Android GK20A driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs2014-01-231-2/+30
| | | | | | As per Android GK20A driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs2014-01-231-15/+15
| | | | | | As per Android GK20A driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: s/playlist/runlist/Ben Skeggs2014-01-231-14/+20
| | | | | | As per Android GK20A driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv108/fifo: initial supportBen Skeggs2014-01-231-54/+58
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2013-11-141-7/+0
| | | | | | | Not required anymore as flips are always done on the kernel's channel, which means we can use a proper software object class instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: make external class definitions into pointersBen Skeggs2013-11-081-2/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: get rid of math.h, replace log2i with order_base_2Ilia Mirkin2013-09-041-2/+1
| | | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nvf0/fifo: enable supportBen Skeggs2013-07-051-1/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs2013-07-011-14/+14
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/ce: link ce2 to its engine, rather than from graphicsBen Skeggs2013-07-011-1/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: copy engine context stored in ramfc, not externallyBen Skeggs2013-07-011-8/+14
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: prevent races between clients updating playlistsBen Skeggs2013-05-201-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50-/fifo: use parent as self for subobjectsBen Skeggs2013-04-261-3/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/nvc0-: use interrupt 31 as an event triggerBen Skeggs2013-02-201-1/+26
| | | | | | | Generated if you try and use fifo method 0x20 on any subchannel, appears that it can be safely masked off without stalling the whole GPU. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: report channel owner in error messagesMarcin Slusarz2013-02-201-6/+23
| | | | | Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: use pr_contMarcin Slusarz2013-02-201-5/+5
| | | | | Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: trigger engine context unload before zeroing context pointerBen Skeggs2012-11-291-4/+3
| | | | | | Fixes a PCE0 page fault noticed on NVD9 during module unload. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: fix the assumption that NVDEV_XXXX is always under 32Martin Peres2012-11-291-4/+4
| | | | | | | | It fixes a bug that would have been introduced when adding more sudevs/engines. Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: allow for future binding of ppp contextsBen Skeggs2012-11-291-0/+2
| | | | | | | No support for the class yet, but will be pulled in with Maarten's Fermi vdec patches. The Kepler PPP class is identical. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/vp: implement initial support for engineBen Skeggs2012-11-291-0/+2
| | | | | | Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/bsp: implement initial support for engineBen Skeggs2012-11-291-0/+2
| | | | | | Will allow use of the engine if firmware (nvXX_fuc084) provided. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: constify instances of nouveau_bitfield and nouveau_enum structsMarcin Slusarz2012-10-031-5/+5
| | | | | Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: use defines instead of hardcoded class idsBen Skeggs2012-10-031-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: have fifo store a unique context identifier at attach timeBen Skeggs2012-10-031-0/+2
| | | | | | | | | | | This value will match something that's easily available from the engine IRQ handlers, and used to lookup the relevant context. Since the changes in how this is done on each generation match when the major PFIFO changes happened, fifo is responsible for calculating the correct value to avoid duplicating the same code among many engine modules. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nve0/fifo: support engine selection when creating fifo channelsBen Skeggs2012-10-031-6/+39
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-031-226/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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