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path: root/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
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* drm/nouveau/fifo: implement nvif event sourceBen Skeggs2014-08-101-14/+3
* drm/nouveau/fifo: allow direct access to channel control registers where poss...Ben Skeggs2014-08-101-0/+1
* drm/nouveau/fifo: audit and version fifo channel classesBen Skeggs2014-08-101-12/+23
* drm/nouveau/core: rework event interfaceBen Skeggs2014-08-101-10/+29
* drm/nouveau/core: allow event source to handle multiple event types per indexBen Skeggs2014-06-111-3/+3
* drm/nve0/fifo: bind intrBen Skeggs2014-03-261-2/+27
* drm/nve0/fifo: attempt to recover from engine ctxsw timeoutsBen Skeggs2014-03-261-0/+44
* drm/nve0/fifo: attempt to recover engines from mmu faultsBen Skeggs2014-03-261-2/+87
* drm/nve0/fifo: allow copy engine channel to be looked up by instanceBen Skeggs2014-03-261-0/+2
* drm/nve0/fifo: use runlist event instead of pollingBen Skeggs2014-03-261-1/+3
* drm/nve0/fifo: allow channels to be marked as unrunnableBen Skeggs2014-03-261-13/+24
* drm/nve0/fifo: single printk for sched error dataBen Skeggs2014-03-261-4/+10
* drm/nve0/fifo: single printk for mmu fault dataBen Skeggs2014-03-261-72/+92
* drm/nve0/fifo: ack pb intr individually after handling each unitBen Skeggs2014-03-261-66/+63
* drm/nve0/fifo: runlist intrBen Skeggs2014-03-261-10/+17
* drm/nve0/fifo: engine intrBen Skeggs2014-03-261-1/+7
* drm/nve0/fifo: mask unhandled intr bits when seen, rather than all intrsBen Skeggs2014-03-261-2/+2
* drm/nve0/fifo: allocate usermem as neededAlexandre Courbot2014-03-261-2/+2
* drm/nouveau: fix ENG_RUNLIST register addressAlexandre Courbot2014-02-181-1/+1
* drm/nouveau/bar: tidy up the subdev and object class definitionsBen Skeggs2014-01-231-0/+1
* drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs2014-01-231-11/+20
* drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs2014-01-231-1/+16
* drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs2014-01-231-11/+87
* drm/nve0/fifo: document more intr status bitsBen Skeggs2014-01-231-5/+72
* drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs2014-01-231-2/+30
* drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs2014-01-231-15/+15
* drm/nve0/fifo: s/playlist/runlist/Ben Skeggs2014-01-231-14/+20
* drm/nv108/fifo: initial supportBen Skeggs2014-01-231-54/+58
* drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2013-11-141-7/+0
* drm/nouveau/fifo: make external class definitions into pointersBen Skeggs2013-11-081-2/+2
* drm/nouveau/core: get rid of math.h, replace log2i with order_base_2Ilia Mirkin2013-09-041-2/+1
* drm/nvf0/fifo: enable supportBen Skeggs2013-07-051-1/+3
* drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs2013-07-011-14/+14
* drm/nve0/ce: link ce2 to its engine, rather than from graphicsBen Skeggs2013-07-011-1/+2
* drm/nve0/fifo: copy engine context stored in ramfc, not externallyBen Skeggs2013-07-011-8/+14
* drm/nve0/fifo: prevent races between clients updating playlistsBen Skeggs2013-05-201-0/+3
* drm/nv50-/fifo: use parent as self for subobjectsBen Skeggs2013-04-261-3/+4
* drm/nouveau/fifo/nvc0-: use interrupt 31 as an event triggerBen Skeggs2013-02-201-1/+26
* drm/nouveau: report channel owner in error messagesMarcin Slusarz2013-02-201-6/+23
* drm/nouveau: use pr_contMarcin Slusarz2013-02-201-5/+5
* drm/nouveau/fifo: trigger engine context unload before zeroing context pointerBen Skeggs2012-11-291-4/+3
* drm/nouveau/core: fix the assumption that NVDEV_XXXX is always under 32Martin Peres2012-11-291-4/+4
* drm/nve0/fifo: allow for future binding of ppp contextsBen Skeggs2012-11-291-0/+2
* drm/nve0/vp: implement initial support for engineBen Skeggs2012-11-291-0/+2
* drm/nve0/bsp: implement initial support for engineBen Skeggs2012-11-291-0/+2
* drm/nouveau: constify instances of nouveau_bitfield and nouveau_enum structsMarcin Slusarz2012-10-031-5/+5
* drm/nouveau/fifo: use defines instead of hardcoded class idsBen Skeggs2012-10-031-1/+1
* drm/nouveau/core: have fifo store a unique context identifier at attach timeBen Skeggs2012-10-031-0/+2
* drm/nve0/fifo: support engine selection when creating fifo channelsBen Skeggs2012-10-031-6/+39
* drm/nouveau: port all engines to new engine module formatBen Skeggs2012-10-031-226/+368
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