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path: root/drivers/gpu/drm/i915/intel_ddi.c
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* drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau2015-05-211-2/+6
* drm/i915/bxt: Move around lane stagger calculationVandana Kannan2015-05-201-20/+20
* drm/i915/bxt: Port PLL programming BUNVandana Kannan2015-05-201-23/+56
* drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira2015-05-201-0/+9
* drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau2015-05-081-32/+32
* drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira2015-05-081-4/+5
* drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal2015-05-081-1/+1
* drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau2015-05-081-13/+13
* drm/i915: fix intel_prepare_ddiImre Deak2015-04-301-10/+18
* drm/i915: factor out ddi_get_encoder_portImre Deak2015-04-301-9/+19
* drm/i915/bxt: VSwing programming sequenceVandana Kannan2015-04-161-1/+119
* drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau2015-04-161-0/+9
* drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau2015-04-161-4/+12
* drm/i915/bxt: Determine programmed frequencySatheeshakrishna M2015-04-161-1/+29
* drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M2015-04-161-1/+1
* drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M2015-04-161-0/+129
* drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M2015-04-161-0/+165
* drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M2015-04-161-2/+2
* drm/i915/skl: Add back HDMI translation tableSonika Jindal2015-04-161-10/+12
* drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan2015-04-161-0/+125
* drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan2015-04-161-0/+2
* Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter2015-04-141-1/+1
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| * drm/i915/bxt: Increase DDI buf idle timeoutVandana Kannan2015-04-091-1/+1
* | drm/i915: Allocate connector state together with the connectorsAnder Conselvan de Oliveira2015-04-131-2/+2
* | drm/i915: Convert the ddi cdclk code to get_display_clock_speedVille Syrjälä2015-03-311-100/+1
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* drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder()Ander Conselvan de Oliveira2015-03-261-9/+15
* drm/i915/skl: Add support for edp 1.4 intermediate frequenciesSonika Jindal2015-03-171-0/+9
* drm/i915/skl: Only use the 800mV+2bB HDMI translation entryDamien Lespiau2015-03-171-16/+14
* drm/i915/skl: Add support for edp1.4 low vswingSonika Jindal2015-02-251-6/+40
* drm/i915: Use pipe_config's cpu_transcoder for reading encoder hw stateAnder Conselvan de Oliveira2015-01-301-1/+1
* drm/i915: Enable/disable DRRSVandana Kannan2015-01-271-0/+2
* drm/i915: Make intel_crtc->config a pointerAnder Conselvan de Oliveira2015-01-271-26/+26
* drm/i915: Pass new_config down do crtc_compute_clockAnder Conselvan de Oliveira2015-01-271-12/+17
* drm/i915: Embedded struct drm_crtc_state in intel_crtc_stateAnder Conselvan de Oliveira2015-01-271-9/+9
* drm/i915: Rename struct intel_crtc_config to intel_crtc_stateAnder Conselvan de Oliveira2015-01-271-5/+5
* drm/i915: Consolidate DDI clock reading out in a single functionDamien Lespiau2014-12-151-6/+7
* drm/i915/skl: Update the DDI translation values for DP/eDP 1.3Damien Lespiau2014-12-031-6/+6
* drm/i915: Don't rely upon encoder->type for infoframe hw state readoutDaniel Vetter2014-11-201-8/+5
* drm/i915/ddi: set has_infoframe flag on DDI too v2Jesse Barnes2014-11-191-0/+8
* drm/i915/ddi: add break in DDI mode select switchJesse Barnes2014-11-181-0/+1
* drm/i915/skl: Use the pipe config DPLL tracking to query the link clockDamien Lespiau2014-11-171-5/+1
* drm/i915/skl: Set the eDP link rate on DPLL0Damien Lespiau2014-11-171-0/+20
* drm/i915: Introduce intel_psr.cRodrigo Vivi2014-11-171-2/+2
* drm/i915/skl: Fix big integer constant sparse warningDamien Lespiau2014-11-141-4/+6
* drm/i915/skl: Apply eDP WA only for gen < 9Vandana Kannan2014-11-141-2/+2
* drm/i915/skl: Implementation of SKL DPLL programmingSatheeshakrishna M2014-11-141-1/+225
* drm/i915/skl: Adjust the port PLL selection codeSatheeshakrishna M2014-11-141-5/+25
* drm/i915/skl: Define shared DPLLs for SkylakeSatheeshakrishna M2014-11-141-1/+125
* drm/i915/skl: Determine enabled PLL and its linkrate/pixel clockSatheeshakrishna M2014-11-141-1/+114
* drm/i915/skl: CD clock back calculation for SKLSatheeshakrishna M2014-11-141-9/+66
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