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path: root/drivers/gpu/drm/i915/intel_ddi.c
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* drm/i915/icl: fix icl_unmap/map_plls_to_portsMahesh Kumar2018-06-071-2/+4
* drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni2018-05-071-4/+94
* drm/i915/icl: Fix the DP Max Voltage for ICLManasi Navare2018-04-301-1/+7
* drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDIManasi Navare2018-04-301-3/+188
* drm/i915/dp: Send DPCD ON for MST before phy_upLyude Paul2018-04-071-2/+6
* drm/i915: use id from intel_shared_dpll.infoLucas De Marchi2018-03-271-4/+4
* drm/i915/icl: Add Voltage swing table for MG PHY DDI BufferManasi Navare2018-03-231-0/+20
* drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.Manasi Navare2018-03-231-0/+99
* drm/i915: Don't spew errors when resetting HDMI scrambling/bit clock ratio failsVille Syrjälä2018-03-231-7/+12
* drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.Dhinakaran Pandiyan2018-03-191-5/+2
* drm/i915/icl: do not save DDI A/E sharing bit for ICLJani Nikula2018-03-091-3/+6
* drm/i915: Track whether the DP link is trained or notVille Syrjälä2018-03-061-0/+2
* drm/i915: Move SST DP link retraining into the ->post_hotplug() hookVille Syrjälä2018-03-061-5/+5
* drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPDVille Syrjälä2018-03-061-0/+146
* drm/i915/icl: remove port A/E lane sharing limitation.Mahesh Kumar2018-03-051-46/+39
* Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2018-03-011-1/+1
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| * drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin2018-02-091-1/+1
* | Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-mi...Dave Airlie2018-02-161-0/+36
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| * drm/i915: Implement HDCP for HDMISean Paul2018-01-081-0/+29
| * drm/i915: Add HDCP framework + base implementationSean Paul2018-01-081-0/+7
* | drm/i915/cnl: Enable DDI-F on Cannonlake.Rodrigo Vivi2018-01-301-0/+4
* | drm/i915: Implement display w/a #1143Ville Syrjälä2018-01-241-0/+42
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* drm/i915: Fix indentation for intel_ddi_clk_selectChris Wilson2017-12-191-2/+2
* drm/i915: Protect DDI port to DPLL map from theoretical race.Rodrigo Vivi2017-12-181-0/+4
* drm/i915/cnl: Mask previous DDI - PLL mappingJames Ausmus2017-12-011-0/+1
* drm/i915: Fix has_audio readout for DDI AVille Syrjälä2017-12-011-10/+10
* drm/i915: Generalize transcoder loopingMika Kahola2017-11-141-4/+6
* drm/i915: Nuke intel_digital_port->portVille Syrjälä2017-11-091-7/+6
* drm/i915: Pass around crtc and connector states for audioVille Syrjälä2017-10-311-2/+4
* drm/i915: Use intel_ddi_get_config() for MSTVille Syrjälä2017-10-301-3/+3
* drm/i915: Pass a crtc state to ddi post_disable from MST codeVille Syrjälä2017-10-301-11/+26
* drm/i915: Eliminate pll->state usage from bxt_calc_pll_link()Ville Syrjälä2017-10-301-12/+5
* drm/i915: Nuke intel_ddi_get_encoder_port()Ville Syrjälä2017-10-301-33/+17
* drm/i915: Stop frobbing with DDI encoder->typeVille Syrjälä2017-10-301-8/+24
* drm/i915: Populate output_types from .get_config()Ville Syrjälä2017-10-301-0/+11
* drm/i915: Fix BXT lane latency optimal setting with MSTVille Syrjälä2017-10-271-2/+1
* drm/i915: Stop using encoder->type in intel_ddi_enable_transcoder_func()Ville Syrjälä2017-10-271-10/+5
* drm/i915: Pass crtc state to intel_prepare_dp_ddi_buffers()Ville Syrjälä2017-10-271-16/+9
* drm/i915: Don't use encoder->type in intel_ddi_set_pipe_settings()Ville Syrjälä2017-10-271-23/+24
* drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä2017-10-251-0/+11
* drm/i915/cnl: Force DDI_A_4_LANES when needed.Rodrigo Vivi2017-10-241-11/+35
* drm/i915: Let's use more enum intel_dpll_id pll_id.Rodrigo Vivi2017-10-201-16/+18
* drm/i915: Drop the redundant hdmi prefix/suffix from a lot of variablesVille Syrjälä2017-10-191-33/+30
* drm/i915: Unify error handling for missing DDI buf trans tablesVille Syrjälä2017-10-191-5/+22
* drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handlingVille Syrjälä2017-10-191-26/+34
* drm/i915: Kill off the BXT buf_trans default_indexVille Syrjälä2017-10-191-46/+34
* drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitlyVille Syrjälä2017-10-191-28/+25
* drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()Ville Syrjälä2017-10-191-24/+45
* drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()Ville Syrjälä2017-10-191-5/+4
* drm/i915: Pass the encoder type explicitly to skl_set_iboost()Ville Syrjälä2017-10-191-35/+22
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