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path: root/drivers/gpu/drm/i915/intel_cdclk.c
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* drm/i915/vlv: Add cdclk workaround for DSIHans de Goede2018-02-141-0/+8
* drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak2018-02-061-5/+17
* BackMerge tag 'v4.15-rc8' into drm-nextDave Airlie2018-01-181-9/+26
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| * drm/i915: Apply Display WA #1183 on skl, kbl, and cflLucas De Marchi2018-01-041-9/+26
* | drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.Maarten Lankhorst2017-11-301-1/+1
* | drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.Rodrigo Vivi2017-10-251-12/+2
* | drm/i915: Perform a central cdclk state sanity checkVille Syrjälä2017-10-251-11/+19
* | drm/i915: Sanity check cdclk in vlv_set_cdclk()Ville Syrjälä2017-10-251-0/+12
* | drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä2017-10-251-1/+45
* | drm/i915: Use cdclk_state->voltage on CNLVille Syrjälä2017-10-251-16/+31
* | drm/i915: Use cdclk_state->voltage on BXT/GLKVille Syrjälä2017-10-251-2/+21
* | drm/i915: Use cdclk_state->voltage on SKL/KBL/CFLVille Syrjälä2017-10-251-7/+36
* | drm/i915: Use cdclk_state->voltage on BDWVille Syrjälä2017-10-251-6/+29
* | drm/i915: Use cdclk_state->voltage on VLV/CHVVille Syrjälä2017-10-251-16/+38
* | drm/i915: Start tracking voltage level in the cdclk stateVille Syrjälä2017-10-251-7/+24
* | drm/i915: Clean up some cdclk switch statementsVille Syrjälä2017-10-251-34/+34
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* drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lockSagar Arun Kamble2017-10-111-20/+20
* drm/i915: Increase poll time for BDW FCLK_DONEMarta Lofstedt2017-09-121-1/+5
* drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()Ville Syrjälä2017-08-311-52/+44
* drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"Ville Syrjälä2017-08-311-98/+104
* drm/i915: reintroduce VLV/CHV PFI programming power domain workaroundGabriel Krisman Bertazi2017-06-291-0/+20
* drm/i915/cnl: Allow dynamic cdclk changes on CNLRodrigo Vivi2017-06-121-4/+56
* drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä2017-06-121-1/+107
* drm/i915/cnl: Implement .set_cdclk() for CNLVille Syrjälä2017-06-121-0/+106
* drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä2017-06-121-1/+55
* drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi2017-06-021-1/+28
* drm/i915: Fix rawclk readout for g4xVille Syrjälä2017-05-051-4/+2
* drm/i915/glk: limit pixel clock to 99% of cdclk workaroundMadhav Chauhan2017-04-061-3/+13
* drm/i915: Implement cdclk restrictions based on Azalia BCLKPandiyan, Dhinakaran2017-03-221-0/+12
* drm/i915/glk: Apply cdclk workaround for DP audioPandiyan, Dhinakaran2017-03-221-6/+11
* drm/i915: Use new atomic iterator macros in cdclkMaarten Lankhorst2017-03-131-1/+1
* drm/i915: remove potentially confusing IS_G4X checksPaulo Zanoni2017-03-071-2/+2
* drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cd...Ville Syrjälä2017-02-081-46/+33
* drm/i915: Nuke the VLV/CHV PFI programming power domain workaroundVille Syrjälä2017-02-081-14/+0
* drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()Ville Syrjälä2017-02-081-1/+4
* drm/i915: Pass the cdclk state to the set_cdclk() functionsVille Syrjälä2017-02-081-30/+48
* drm/i915: Pass dev_priv to remainder of the cdclk functionsVille Syrjälä2017-02-081-15/+10
* drm/i915: Track full cdclk state for the logical and actual cdclk frequenciesVille Syrjälä2017-02-081-45/+78
* drm/i915: Start moving the cdclk stuff into a distinct state structureVille Syrjälä2017-02-081-156/+226
* drm/i915: Pass computed vco to bxt_set_cdclk()Ville Syrjälä2017-02-081-14/+19
* drm/i915: Move most cdclk/rawclk related code to intel_cdclk.cVille Syrjälä2017-02-081-0/+1794
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