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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bitsPatrik Jakobsson2013-03-061-2/+2
* drm/i915: Implement pipe CSC based limited range RGB outputVille Syrjälä2013-02-201-1/+51
* drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+Ville Syrjälä2013-02-201-0/+1
* drm/i915: Preserve the DDI link reversal configurationDamien Lespiau2013-02-201-0/+1
* drm/i915: Preserve the FDI line reversal override bit on CPTDamien Lespiau2013-02-201-1/+1
* drm/i915: detect wrong MCH watermark valuesDaniel Vetter2013-02-201-0/+4
* drm/i915: unify HDMI/DP hpd definitionsDaniel Vetter2013-02-151-19/+9
* drm/i915: Fix RC6VIDS encode/decodeBen Widawsky2013-02-141-2/+2
* Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...Dave Airlie2013-02-081-0/+3
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| * drm/i915: Disable AsyncFlip performance optimisationsChris Wilson2013-01-231-0/+1
| * drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-stateChris Wilson2013-01-151-0/+2
* | drm/i915: Introduce i915_vgacntrl_reg()Ville Syrjälä2013-01-311-0/+2
* | drm/i915: Fix CAGF for HSWBen Widawsky2013-01-311-0/+2
* | drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky2013-01-281-0/+1
* | drm/i915: fix intel_init_power_wellsPaulo Zanoni2013-01-261-4/+4
* | drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä2013-01-261-13/+13
* | drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä2013-01-261-2/+8
* | drm/i915: PLL registers need an offset on VLVVille Syrjälä2013-01-261-4/+4
* | drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä2013-01-241-4/+6
* | drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä2013-01-241-5/+5
* | drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä2013-01-241-1/+1
* | drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä2013-01-241-1/+1
* | drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä2013-01-241-2/+2
* | drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä2013-01-241-18/+18
* | drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä2013-01-241-2/+2
* | drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä2013-01-241-3/+3
* | drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä2013-01-241-2/+2
* | drm/i915: DSPFW registers need an offset on VLVVille Syrjälä2013-01-241-3/+3
* | drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä2013-01-241-2/+2
* | drm/i915: Cursor registers need an offset on VLVVille Syrjälä2013-01-241-6/+6
* | drm/i915: Pipe registers need an offset on VLVVille Syrjälä2013-01-241-10/+10
* | drm/i915: Primary plane registers need an offset on VLVVille Syrjälä2013-01-241-18/+18
* | drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä2013-01-241-16/+16
* | drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä2013-01-241-6/+6
* | drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä2013-01-241-11/+11
* | drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä2013-01-241-1/+1
* | drm/i915: Fix RGB color range property for PCH platformsVille Syrjälä2013-01-201-0/+1
* | drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLVVille Syrjälä2013-01-171-2/+2
* | Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet...Dave Airlie2013-01-171-40/+18
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| * drm/i915: clean up PIPECONF bpc #definesDaniel Vetter2012-12-171-10/+5
| * drm/i915: Cleanup SHOTPLUG_CTL status bits definitionsDamien Lespiau2012-12-141-9/+12
| * drm/i915: Remove duplicate and unused register #defines in i915_reg.hDexuan Cui2012-12-061-4/+0
| * drm/i915: remove duplicate register #definesDaniel Vetter2012-11-291-17/+1
* | drm/i915: Implement WaSetupGtModeTdRowDispatchDaniel Vetter2012-12-171-1/+2
* | drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabledDaniel Vetter2012-12-171-0/+1
* | drm/i915: set the LPT FDI RX polarity reversal bit when neededPaulo Zanoni2012-12-101-0/+1
* | drm/i915: add lpt_init_pch_refclkPaulo Zanoni2012-12-101-1/+5
* | drm/i915: add support for mPHY destination on intel_sbi_{read, write}Paulo Zanoni2012-12-101-0/+4
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* drm/i915: make the panel fitter work on pipes B and C on IVBPaulo Zanoni2012-11-211-0/+2
* drm/i915: don't intel_crt_init if DDI A has 4 lanesPaulo Zanoni2012-11-211-0/+1
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