| Commit message (Expand) | Author | Age | Files | Lines |
* | clk: tegra: Rework pll_u | Peter De Schrijver | 2017-03-20 | 1 | -174/+0 |
* | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker | 2016-06-30 | 1 | -0/+505 |
* | clk: tegra: Fix pllre Tegra210 and add pll_re_out1 | Rhyland Klein | 2016-04-28 | 1 | -0/+46 |
* | clk: tegra: Fix PLLE SS coefficients | Mark Kuo | 2016-02-02 | 1 | -6/+12 |
* | clk: tegra: Fix typos around clearing PLLE bits during enable | Rhyland Klein | 2016-02-02 | 1 | -2/+2 |
* | clk: tegra: Do not disable PLLE when under hardware control | Mark Kuo | 2016-02-02 | 1 | -7/+15 |
* | clk: tegra: pll: Fix potential sleeping-while-atomic | Andrew Bresticker | 2016-02-02 | 1 | -3/+3 |
* | clk: tegra: Read correct IDDQ register in PLL_SS registration | Bill Huang | 2015-12-17 | 1 | -4/+7 |
* | clk: tegra: Fix WARN_ON in PLL_RE registration | Bill Huang | 2015-12-17 | 1 | -1/+2 |
* | clk: tegra: pll: Fix issues with rates for VCO PLLs | Andrew Bresticker | 2015-12-17 | 1 | -4/+12 |
* | clk: tegra: Add support for Tegra210 clocks | Rhyland Klein | 2015-12-17 | 1 | -0/+5 |
* | clk: tegra: pll: Add logic for SS | Bill Huang | 2015-12-17 | 1 | -1/+24 |
* | clk: tegra: pll: Add dyn_ramp callback | Rhyland Klein | 2015-12-17 | 1 | -0/+7 |
* | clk: tegra: pll: Add Set_default logic | Bill Huang | 2015-12-17 | 1 | -11/+28 |
* | clk: tegra: pll: Adjust vco_min if SDM present | Bill Huang | 2015-12-17 | 1 | -0/+28 |
* | clk: tegra: pll: Add support for PLLMB for Tegra210 | Rhyland Klein | 2015-12-17 | 1 | -5/+43 |
* | clk: tegra: pll: Add specialized logic for Tegra210 | Rhyland Klein | 2015-12-17 | 1 | -2/+322 |
* | clk: tegra: pll: Update PLLM handling | Danny Huang | 2015-11-20 | 1 | -49/+7 |
* | clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate | Rhyland Klein | 2015-11-20 | 1 | -41/+50 |
* | clk: tegra: pll: Add code to handle if resets are supported by PLL | Bill Huang | 2015-11-20 | 1 | -0/+12 |
* | clk: tegra: pll: Add logic for out-of-table rates for T210 | Rhyland Klein | 2015-11-20 | 1 | -2/+22 |
* | clk: tegra: pll: Add logic for handling SDM data | Rhyland Klein | 2015-11-20 | 1 | -1/+65 |
* | clk: tegra: pll: Don't unconditionally set LOCK flags | Rhyland Klein | 2015-11-20 | 1 | -9/+2 |
* | clk: tegra: pll: Update warning message | Rhyland Klein | 2015-11-20 | 1 | -1/+2 |
* | clk: tegra: pll: Simplify clk_enable_path | Rhyland Klein | 2015-11-20 | 1 | -54/+22 |
* | clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header | Rhyland Klein | 2015-11-20 | 1 | -0/+5 |
* | clk: tegra: Constify pdiv-to-hw mappings | Thierry Reding | 2015-11-20 | 1 | -3/+3 |
* | clk: tegra: Miscellaneous coding style cleanups | Thierry Reding | 2015-11-18 | 1 | -3/+3 |
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) | Stephen Boyd | 2015-08-24 | 1 | -4/+4 |
* | clk: tegra: Convert to clk_hw based provider APIs | Stephen Boyd | 2015-08-24 | 1 | -5/+5 |
* | clk: tegra: Properly include clk.h | Stephen Boyd | 2015-07-20 | 1 | -1/+1 |
* | clk: tegra: Remove needless initializations | Thierry Reding | 2015-04-10 | 1 | -3/+3 |
* | clk: tegra: Various whitespace cleanups | Thierry Reding | 2015-04-10 | 1 | -0/+1 |
* | clk: tegra: Add support for the Tegra132 CAR IP block | Paul Walmsley | 2015-02-02 | 1 | -3/+7 |
* | clk: tegra: Fix order of arguments in WARN | Tomeu Vizoso | 2015-02-02 | 1 | -4/+4 |
* | clk: tegra: Use XUSB-compatible SATA PLL sequence | Mikko Perttunen | 2014-07-08 | 1 | -0/+11 |
* | clk: tegra: Enable hardware control of SATA PLL | Mikko Perttunen | 2014-06-25 | 1 | -0/+8 |
* | Merge branch 'clk-fixes' into clk-next | Mike Turquette | 2014-05-28 | 1 | -21/+43 |
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| * | Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijv... | Mike Turquette | 2014-05-27 | 1 | -21/+43 |
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| | * | clk: tegra: Fix enabling of PLLE | Thierry Reding | 2014-04-17 | 1 | -1/+1 |
| | * | clk: tegra: Introduce divider mask and shift helpers | Thierry Reding | 2014-04-17 | 1 | -20/+24 |
| | * | clk: tegra: Fix PLLE programming | Thierry Reding | 2014-04-17 | 1 | -6/+24 |
* | | | clk: tegra: Enable hardware control of PLLE | Jim Lin | 2014-05-22 | 1 | -1/+32 |
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* | | clk: tegra: Fix wrong value written to PLLE_AUX | Tuomas Tynkkynen | 2014-05-16 | 1 | -1/+1 |
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* | clk: tegra: Staticize local variables in clk-pll.c | Sachin Kamat | 2013-12-19 | 1 | -6/+6 |
* | clk: tegra: fix __clk_lookup() return value checks | Wei Yongjun | 2013-11-28 | 1 | -4/+4 |
* | clk: tegra: Do not print errors for clk_round_rate() | Thierry Reding | 2013-11-28 | 1 | -6/+3 |
* | clk: tegra: Add support for PLLSS | Peter De Schrijver | 2013-11-26 | 1 | -2/+121 |
* | clk: tegra: move fields to tegra_clk_pll_params | Peter De Schrijver | 2013-11-26 | 1 | -79/+59 |
* | clk: tegra: use pll_ref as the pll_e parent | Peter De Schrijver | 2013-11-26 | 1 | -3/+5 |