summaryrefslogtreecommitdiffstats
path: root/arch/xtensa/boot/dts/xtfpga.dtsi
Commit message (Expand)AuthorAgeFilesLines
* xtensa: xtfpga: fix earlycon endiannessMax Filippov2016-03-111-1/+1
* xtensa: xtfpga: fix i2c controller register width and endiannessMax Filippov2016-03-111-1/+2
* xtensa: xtfpga: fix ethernet controller endiannessMax Filippov2016-03-111-0/+1
* xtensa: xtfpga: fix serial port register width and endiannessMax Filippov2016-03-111-0/+2
* xtensa: xtfpga: add audio card to xtfpga DTSMax Filippov2015-02-071-0/+64
* xtensa: xtfpga: introduce SoC I/O busMax Filippov2014-04-061-15/+22
* xtensa: xtfpga: set ethoc clock frequencyMax Filippov2014-02-211-0/+1
* xtensa: xtfpga: use common clock frameworkMax Filippov2014-02-211-3/+8
* xtensa: standardize devicetree cpu compatible stringsBaruch Siach2014-01-151-2/+2
* xtensa: move built-in PIC to drivers/irqchipMax Filippov2014-01-141-1/+1
* xtensa: add XTFPGA DTSMax Filippov2012-12-181-0/+56
OpenPOWER on IntegriCloud