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| author | Mark Zhang <markz@nvidia.com> | 2014-12-09 14:59:59 +0800 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2015-02-02 16:22:34 +0200 |
| commit | b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 (patch) | |
| tree | 4b0c4d9b987aa11332a5a2f774c0beb7c78f0a6e /include | |
| parent | 08acae34e8dadaa8c3a0a432760555bba1db8bfb (diff) | |
| download | op-kernel-dev-b270491eb9a033a1ab6c66e778c9dd3e3a4f7639.zip op-kernel-dev-b270491eb9a033a1ab6c66e778c9dd3e3a4f7639.tar.gz | |
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.
So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/tegra124-car-common.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index aeb52df..ae2eb17 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -297,7 +297,7 @@ #define TEGRA124_CLK_PLL_C4 270 #define TEGRA124_CLK_PLL_DP 271 #define TEGRA124_CLK_PLL_E_MUX 272 -/* 273 */ +#define TEGRA124_CLK_PLLD_DSI 273 /* 274 */ /* 275 */ /* 276 */ @@ -334,8 +334,8 @@ #define TEGRA124_CLK_CLK_OUT_1_MUX 306 #define TEGRA124_CLK_CLK_OUT_2_MUX 307 #define TEGRA124_CLK_CLK_OUT_3_MUX 308 -#define TEGRA124_CLK_DSIA_MUX 309 -#define TEGRA124_CLK_DSIB_MUX 310 +/* 309 */ +/* 310 */ #define TEGRA124_CLK_SOR0_LVDS 311 #define TEGRA124_CLK_XUSB_SS_DIV2 312 |
