From b270491eb9a033a1ab6c66e778c9dd3e3a4f7639 Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Tue, 9 Dec 2014 14:59:59 +0800 Subject: clk: tegra: Define PLLD_DSI and remove dsia(b)_mux PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver Signed-off-by: Mark Zhang --- include/dt-bindings/clock/tegra124-car-common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index aeb52df..ae2eb17 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -297,7 +297,7 @@ #define TEGRA124_CLK_PLL_C4 270 #define TEGRA124_CLK_PLL_DP 271 #define TEGRA124_CLK_PLL_E_MUX 272 -/* 273 */ +#define TEGRA124_CLK_PLLD_DSI 273 /* 274 */ /* 275 */ /* 276 */ @@ -334,8 +334,8 @@ #define TEGRA124_CLK_CLK_OUT_1_MUX 306 #define TEGRA124_CLK_CLK_OUT_2_MUX 307 #define TEGRA124_CLK_CLK_OUT_3_MUX 308 -#define TEGRA124_CLK_DSIA_MUX 309 -#define TEGRA124_CLK_DSIB_MUX 310 +/* 309 */ +/* 310 */ #define TEGRA124_CLK_SOR0_LVDS 311 #define TEGRA124_CLK_XUSB_SS_DIV2 312 -- cgit v1.1