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| author | Sohil Mehta <sohil.mehta@intel.com> | 2017-12-20 11:59:26 -0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2018-01-17 15:02:50 +0100 |
| commit | f1ac10c24efbbcba0f8dae37ee90d45847f5c5af (patch) | |
| tree | dfc517909ee0e7bd723dd37dace984008ba51dab /drivers/iommu/intel-svm.c | |
| parent | 59103caa6839592788e7ad58b35863aac034631a (diff) | |
| download | op-kernel-dev-f1ac10c24efbbcba0f8dae37ee90d45847f5c5af.zip op-kernel-dev-f1ac10c24efbbcba0f8dae37ee90d45847f5c5af.tar.gz | |
iommu/vt-d: Add a check for 5-level paging support
Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/intel-svm.c')
| -rw-r--r-- | drivers/iommu/intel-svm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index e9a56ad..b43dc1e 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) !cap_fl1gp_support(iommu->cap)) return -EINVAL; + if (cpu_feature_enabled(X86_FEATURE_LA57) && + !cap_5lp_support(iommu->cap)) + return -EINVAL; + /* Start at 2 because it's defined as 2^(1+PSS) */ iommu->pasid_max = 2 << ecap_pss(iommu->ecap); |
