From f1ac10c24efbbcba0f8dae37ee90d45847f5c5af Mon Sep 17 00:00:00 2001 From: Sohil Mehta Date: Wed, 20 Dec 2017 11:59:26 -0800 Subject: iommu/vt-d: Add a check for 5-level paging support Add a check to verify IOMMU 5-level paging support. If the CPU supports supports 5-level paging but the IOMMU does not support it then disable SVM by not allocating PASID tables. Signed-off-by: Sohil Mehta Signed-off-by: Joerg Roedel --- drivers/iommu/intel-svm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/iommu/intel-svm.c') diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index e9a56ad..b43dc1e 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) !cap_fl1gp_support(iommu->cap)) return -EINVAL; + if (cpu_feature_enabled(X86_FEATURE_LA57) && + !cap_5lp_support(iommu->cap)) + return -EINVAL; + /* Start at 2 because it's defined as 2^(1+PSS) */ iommu->pasid_max = 2 << ecap_pss(iommu->ecap); -- cgit v1.1