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| author | Imre Deak <imre.deak@intel.com> | 2016-06-13 16:44:32 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-06-13 18:46:08 +0300 |
| commit | e4c49e0f1069b338a28622595dfaf6616f7662c1 (patch) | |
| tree | e8f3d3e1bb158e0c099a680912764e8ca820c5f7 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 94bb489c89c4ca7dc36bfbe50e77f26d8458e347 (diff) | |
| download | op-kernel-dev-e4c49e0f1069b338a28622595dfaf6616f7662c1.zip op-kernel-dev-e4c49e0f1069b338a28622595dfaf6616f7662c1.tar.gz | |
drm/i915/bxt: Wait for PHY1 GRC calibration synchronously
A follow-up patch moves the PHY enabling to the power well code where
enabling/disabling the PHYs will happen independently. Because of this
waiting for the GRC calibration in PHY1 asynchronously would need some
additional logic. Instead of adding that let's keep things simple for now
and wait synchronously. My measurements showed that the calibration
takes ~4ms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 022b41d..b10c7b5 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1899,8 +1899,6 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, * the corresponding calibrated value from PHY1, and disable * the automatic calibration on PHY0. */ - broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); - val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, DPIO_PHY1); grc_code = val << GRC_CODE_FAST_SHIFT | @@ -1912,14 +1910,13 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, val |= GRC_DIS | GRC_RDY_OVRD; I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); } - /* - * During PHY1 init delay waiting for GRC calibration to finish, since - * it can happen in parallel with the subsequent PHY0 init. - */ val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); val |= COMMON_RESET_DIS; I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); + + if (phy == DPIO_PHY1) + broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); } void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) @@ -1927,12 +1924,6 @@ void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) /* Enable PHY1 first since it provides Rcomp for PHY0 */ broxton_phy_init(dev_priv, DPIO_PHY1); broxton_phy_init(dev_priv, DPIO_PHY0); - - /* - * If BIOS enabled only PHY0 and not PHY1, we skipped waiting for the - * PHY1 GRC calibration to finish, so wait for it here. - */ - broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); } static void broxton_phy_uninit(struct drm_i915_private *dev_priv, |
