diff options
| author | Chao Xie <chao.xie@marvell.com> | 2014-10-31 10:13:46 +0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2014-11-12 16:34:00 -0800 |
| commit | cdce35460f5bd929cbcb75a8f436776bd0112f49 (patch) | |
| tree | 00f8559dd38991327e643c86701c83faf5ceff4c /drivers/clk/mmp/Makefile | |
| parent | ee81f4ee2a3632a2d7928f680c4af8243a18762f (diff) | |
| download | op-kernel-dev-cdce35460f5bd929cbcb75a8f436776bd0112f49.zip op-kernel-dev-cdce35460f5bd929cbcb75a8f436776bd0112f49.tar.gz | |
clk: mmp: add mmp private gate clock
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. It is not always that "1" is to enable while "0" is to disable
when write register.
So we have to define the "mask", "enable_val", "disable_val" for
this kind of gate clock.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/mmp/Makefile')
| -rw-r--r-- | drivers/clk/mmp/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 8bfee860..2855f7b 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -2,7 +2,7 @@ # Makefile for mmp specific clk # -obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o +obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o |
