From cdce35460f5bd929cbcb75a8f436776bd0112f49 Mon Sep 17 00:00:00 2001 From: Chao Xie Date: Fri, 31 Oct 2014 10:13:46 +0800 Subject: clk: mmp: add mmp private gate clock Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register. So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock. Signed-off-by: Chao Xie Acked-by: Haojian Zhuang Signed-off-by: Michael Turquette --- drivers/clk/mmp/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/mmp/Makefile') diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 8bfee860..2855f7b 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -2,7 +2,7 @@ # Makefile for mmp specific clk # -obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o +obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o -- cgit v1.1