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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 16:35:29 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 16:35:29 -0700
commit640414171818c6293c23e74a28d1c69b2a1a7fe5 (patch)
treecb3b10578f0ae39eac2930ce3b2c8a1616f5ba70 /arch/arm/boot/dts
parentfa91515cbf2375a64c8bd0a033a05b0859dff591 (diff)
parenta2bdc32a527e817fdfa6c56eaa6c70f217da6c6c (diff)
downloadop-kernel-dev-640414171818c6293c23e74a28d1c69b2a1a7fe5.zip
op-kernel-dev-640414171818c6293c23e74a28d1c69b2a1a7fe5.tar.gz
Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Kevin Hilman: "These are changes that arrived a little late before the merge window, or had dependencies on previous branches. Highlights: - ux500: misc. cleanup, fixup I2C devices - exynos: DT updates for RTC; PM updates - at91: DT updates for NAND; new platforms added to generic defconfig - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks - highbank: LPAE fixes, select necessary ARM errata - omap: PM fixes and improvements; OMAP5 mailbox support - omap: basic support for new DRA7xx SoCs" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) ARM: dts: vexpress: Add CCI node to TC2 device-tree ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: highbank: clean-up some unused includes ARM: sun7i: Enable the A20 clocks in the DTSI ARM: sun6i: Enable clock support in the DTSI ARM: sun5i: dt: Use the A10s gates in the DTSI ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: dts: add ADC device tree node for exynos5420/5250 ARM: dts: Add RTC DT node to Exynos5420 SoC ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC ARM: dts: Fix the RTC DT node name for Exynos5250 irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi14
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi19
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi36
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts2
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi161
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi157
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts25
15 files changed, 467 insertions, 57 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e02f1b..cc0f1fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -231,6 +231,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a13-olinuxino.dtb \
sun6i-a31-colombus.dtb \
+ sun7i-a20-cubieboard2.dtb \
sun7i-a20-olinuxino-micro.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..074739d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
interrupts = <0 54 0>;
};
- rtc {
+ rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b0..cee55fa 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -538,10 +538,6 @@
};
};
- rtc {
- status = "okay";
- };
-
usb_hub_bus {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index e79331d..fd711e2 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,10 +171,6 @@
};
};
- rtc {
- status = "okay";
- };
-
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7e2d34..7d7cc77 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -180,9 +180,10 @@
clock-names = "mfc";
};
- rtc {
+ rtc@101E0000 {
clocks = <&clock 337>;
clock-names = "rtc";
+ status = "okay";
};
tmu@10060000 {
@@ -638,4 +639,15 @@
clocks = <&clock 133>, <&clock 339>;
clock-names = "sclk_fimd", "fimd";
};
+
+ adc: adc@12D10000 {
+ compatible = "samsung,exynos-adc-v1";
+ reg = <0x12D10000 0x100>, <0x10040718 0x4>;
+ interrupts = <0 106 0>;
+ clocks = <&clock 303>;
+ clock-names = "adc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..d537cd7 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -180,6 +180,12 @@
interrupts = <0 47 0>;
};
+ rtc@101E0000 {
+ clocks = <&clock 317>;
+ clock-names = "rtc";
+ status = "okay";
+ };
+
serial@12C00000 {
clocks = <&clock 257>, <&clock 128>;
clock-names = "uart", "clk_uart_baud0";
@@ -218,4 +224,15 @@
clocks = <&clock 147>, <&clock 421>;
clock-names = "sclk_fimd", "fimd";
};
+
+ adc: adc@12D10000 {
+ compatible = "samsung,exynos-adc-v2";
+ reg = <0x12D10000 0x100>, <0x10040720 0x4>;
+ interrupts = <0 106 0>;
+ clocks = <&clock 270>;
+ clock-names = "adc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index ff63fbb..b7f4961 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1034,21 +1034,30 @@
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
+ ranges;
reg = < 0x60000000 0x01000000 /* EBI CS3 */
0xffffc070 0x00000490 /* SMC PMECC regs */
0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
- 0x00100000 0x00100000 /* ROM code */
- 0x70000000 0x10000000 /* NFC Command Registers */
- 0xffffc000 0x00000070 /* NFC HSMC regs */
- 0x00200000 0x00100000 /* NFC SRAM banks */
+ 0x00110000 0x00018000 /* ROM code */
>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand0_ale_cle>;
- atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
+ atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
status = "disabled";
+
+ nfc@70000000 {
+ compatible = "atmel,sama5d3-nfc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <
+ 0x70000000 0x10000000 /* NFC Command Registers */
+ 0xffffc000 0x00000070 /* NFC HSMC regs */
+ 0x00200000 0x00100000 /* NFC SRAM banks */
+ >;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f80508..31ed9e3 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -47,8 +47,6 @@
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
- atmel,has-nfc;
- atmel,use-nfc-sram;
nand-on-flash-bbt;
status = "okay";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee0ff9b..3b4a057 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
+ compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
+ "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
+ "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
};
apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
+ compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
+ "apb0_ir", "apb0_keypad";
};
/* dummy is pll62 */
@@ -145,15 +140,12 @@
apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
+ compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3";
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 99c4b18..e5adae3 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -24,6 +24,8 @@
soc@01c00000 {
uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d076ec..f244f5f 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -51,13 +51,137 @@
clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges;
- osc: oscillator {
+ osc24M: osc24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ pll1: pll1@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ };
+
+ /*
+ * This is a dummy clock, to be used as placeholder on
+ * other mux clocks when a specific parent clock is not
+ * yet implemented. It should be dropped when the driver
+ * is complete.
+ */
+ pll6: pll6 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cpu: cpu@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ };
+
+ axi: axi@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ };
+
+ ahb1_mux: ahb1_mux@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+ };
+
+ ahb1: ahb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1_mux>;
+ };
+
+ ahb1_gates: ahb1_gates@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+ "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+ "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+ "ahb1_nand0", "ahb1_sdram",
+ "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+ "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+ "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+ "ahb1_ehci1", "ahb1_ohci0",
+ "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+ "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+ "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+ "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+ "ahb1_drc0", "ahb1_drc1";
+ };
+
+ apb1: apb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ };
+
+ apb1_gates: apb1_gates@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_digital_mic",
+ "apb1_pio", "apb1_daudio0",
+ "apb1_daudio1";
+ };
+
+ apb2_mux: apb2_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+ };
+
+ apb2: apb2@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-apb2-div-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb2_mux>;
+ };
+
+ apb2_gates: apb2_gates@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+ reg = <0x01c2006c 0x8>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2", "apb2_uart3",
+ "apb2_uart4", "apb2_uart5";
+ };
};
soc@01c00000 {
@@ -66,6 +190,25 @@
#size-cells = <1>;
ranges;
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun6i-a31-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
timer@01c20c00 {
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0xa0>;
@@ -74,7 +217,7 @@
<0 20 1>,
<0 21 1>,
<0 22 1>;
- clocks = <&osc>;
+ clocks = <&osc24M>;
};
wdt1: watchdog@01c20ca0 {
@@ -88,7 +231,7 @@
interrupts = <0 0 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 16>;
status = "disabled";
};
@@ -98,7 +241,7 @@
interrupts = <0 1 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 17>;
status = "disabled";
};
@@ -108,7 +251,7 @@
interrupts = <0 2 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 18>;
status = "disabled";
};
@@ -118,7 +261,7 @@
interrupts = <0 3 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 19>;
status = "disabled";
};
@@ -128,7 +271,7 @@
interrupts = <0 4 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 20>;
status = "disabled";
};
@@ -138,7 +281,7 @@
interrupts = <0 5 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc>;
+ clocks = <&apb2_gates 21>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 0000000..31b76f0
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+
+/ {
+ model = "Cubietech Cubieboard2";
+ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
+
+ soc@01c00000 {
+ pinctrl@01c20800 {
+ led_pins_cubieboard2: led_pins@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cubieboard2>;
+
+ blue {
+ label = "cubieboard2:blue:usr";
+ gpios = <&pio 7 21 0>;
+ };
+
+ green {
+ label = "cubieboard2:green:usr";
+ gpios = <&pio 7 20 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index d339584..34a6c02 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,16 +19,43 @@
compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
soc@01c00000 {
+ pinctrl@01c20800 {
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <1>;
+ allwinner,pull = <0>;
+ };
+ };
+
uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
uart6: serial@01c29800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins_a>;
status = "okay";
};
uart7: serial@01c29c00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
status = "okay";
};
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxino>;
+
+ green {
+ label = "a20-olinuxino-micro:green:usr";
+ gpios = <&pio 7 2 0>;
+ default-state = "on";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 3339151..999ff45 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -44,7 +44,8 @@
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
- compatible = "fixed-clock";
+ compatible = "allwinner,sun4i-osc-clk";
+ reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
};
@@ -53,6 +54,111 @@
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+
+ pll1: pll1@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ };
+
+ /*
+ * This is a dummy clock, to be used as placeholder on
+ * other mux clocks when a specific parent clock is not
+ * yet implemented. It should be dropped when the driver
+ * is complete.
+ */
+ pll6: pll6 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ };
+
+ ahb_gates: ahb_gates@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_spi3", "ahb_sata",
+ "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+ "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+ "ahb_mali";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ };
+
+ apb0_gates: apb0_gates@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis0", "apb0_iis1",
+ "apb0_pio", "apb0_ir0", "apb0_ir1",
+ "apb0_iis2", "apb0_keypad";
+ };
+
+ apb1_mux: apb1_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6>, <&osc32k>;
+ };
+
+ apb1: apb1@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb1_mux>;
+ };
+
+ apb1_gates: apb1_gates@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_i2c3", "apb1_can",
+ "apb1_scr", "apb1_ps20", "apb1_ps21",
+ "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6", "apb1_uart7";
+ };
};
soc@01c00000 {
@@ -61,6 +167,39 @@
#size-cells = <1>;
ranges;
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun7i-a20-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 28 1>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB22", "PB23";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart6_pins_a: uart6@0 {
+ allwinner,pins = "PI12", "PI13";
+ allwinner,function = "uart6";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart7_pins_a: uart7@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "uart7";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
timer@01c20c00 {
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0x90>;
@@ -84,7 +223,7 @@
interrupts = <0 1 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 16>;
status = "disabled";
};
@@ -94,7 +233,7 @@
interrupts = <0 2 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 17>;
status = "disabled";
};
@@ -104,7 +243,7 @@
interrupts = <0 3 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 18>;
status = "disabled";
};
@@ -114,7 +253,7 @@
interrupts = <0 4 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 19>;
status = "disabled";
};
@@ -124,7 +263,7 @@
interrupts = <0 17 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 20>;
status = "disabled";
};
@@ -134,7 +273,7 @@
interrupts = <0 18 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 21>;
status = "disabled";
};
@@ -144,7 +283,7 @@
interrupts = <0 19 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 22>;
status = "disabled";
};
@@ -154,7 +293,7 @@
interrupts = <0 20 1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&osc24M>;
+ clocks = <&apb1_gates 23>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 759b0cd..15f98cb 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
+ cci-control-port = <&cci_control1>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
+ cci-control-port = <&cci_control1>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ cci-control-port = <&cci_control2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
+ cci-control-port = <&cci_control2>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
+ cci-control-port = <&cci_control2>;
};
};
@@ -104,6 +109,26 @@
interrupts = <1 9 0xf04>;
};
+ cci@2c090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2c090000 0 0x1000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+ cci_control1: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control2: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+ };
+
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
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