From 140e1721d108227cc3129c12dca1c5f8ccc7fb39 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 12 Mar 2013 22:16:05 +0100 Subject: ARM: sunxi: dt: Add PIO controller to A31 DTSI The A31 has a different set of pins than the one found on the A10 and A13. Now that we have support for the A31 pin set in the pinctrl driver, we can enable it in the DTSI with its own compatible. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 4d076ec..902b1e6 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -66,6 +66,18 @@ #size-cells = <1>; ranges; + pio: pinctrl@01c20800 { + compatible = "allwinner,sun6i-a31-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>; + clocks = <&osc>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0xa0>; -- cgit v1.1 From ab4238cd0513d25d0dec915880422f0633f4b965 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 22 Jun 2013 23:56:40 +0200 Subject: ARM: sun6i: Add UART0 muxing options Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 902b1e6..dc5da4f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -76,6 +76,13 @@ #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.1 From 69fb3c047e720a317757f54be08679ab7caeaf91 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 22 Jun 2013 23:57:27 +0200 Subject: ARM: sun6i: colombus: Add uart0 muxing Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 99c4b18..e5adae3 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -24,6 +24,8 @@ soc@01c00000 { uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; }; -- cgit v1.1 From 17eac031b7cad5eff7610639041967d06aa1e553 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 24 Jul 2013 23:46:11 +0200 Subject: ARM: sun7i: Add the PIO controller node to the DTSI The PIO controller is responsible for the GPIO/muxing/external interrupts handling. Now that we have support for the A20 pin set in the pinctrl driver, we can start using it in the DTSI. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3339151..980ec75 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -61,6 +61,18 @@ #size-cells = <1>; ranges; + pio: pinctrl@01c20800 { + compatible = "allwinner,sun7i-a20-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <0 28 1>; + clocks = <&osc24M>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0x90>; -- cgit v1.1 From 9f229ba957c3119fd1965c07c56d1618ed2d9b89 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 00:09:47 +0200 Subject: ARM: sun7i: DT: Add UART muxing options to the DTSI The UARTs on the A20 can be muxed to several pins. Add a few options to the DTSI so that we can start using them in the boards' DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 980ec75..f4e4524 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -71,6 +71,27 @@ #address-cells = <1>; #size-cells = <0>; #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB22", "PB23"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart6_pins_a: uart6@0 { + allwinner,pins = "PI12", "PI13"; + allwinner,function = "uart6"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart7_pins_a: uart7@0 { + allwinner,pins = "PI20", "PI21"; + allwinner,function = "uart7"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.1 From 2fff6ac079c80201d5e9091e9773b99aef559112 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 00:10:53 +0200 Subject: ARM: sun7i: a20-olinuxino: Enable UARTs muxing Instead of relying on the bootloader to mux the UART pins properly, do it on our own and register the rightful pins for the A20-olinuxino in the DT using pinctrl. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index d339584..4d988df 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -20,14 +20,20 @@ soc@01c00000 { uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; uart6: serial@01c29800 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins_a>; status = "okay"; }; uart7: serial@01c29c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; status = "okay"; }; }; -- cgit v1.1 From 6e487da76833c4a8cccec673663118307d0d671b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 00:12:45 +0200 Subject: ARM: sun7i: a20-olinuxino: Enable the user LED The A20-olinuxino Micro has a LED connected to the PH2 pin. Use the gpio-led driver to enable the control over this LED. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 4d988df..34a6c02 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -19,6 +19,15 @@ compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; soc@01c00000 { + pinctrl@01c20800 { + led_pins_olinuxino: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -37,4 +46,16 @@ status = "okay"; }; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; + + green { + label = "a20-olinuxino-micro:green:usr"; + gpios = <&pio 7 2 0>; + default-state = "on"; + }; + }; }; -- cgit v1.1 From 82abe5294aeadc42508c7944f3a9aec0eece214c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 12:19:16 +0200 Subject: ARM: sun7i: Add Cubieboard2 Device Tree The Cubieboard2 is the successor of the first Cubieboard, and shares the same hardware, except that the Allwinner A10 found initially has been replaced by an Allwinner A20. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 53 +++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm/boot/dts/sun7i-a20-cubieboard2.dts (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 54ec24c..ec1a3f5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -213,6 +213,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb \ sun6i-a31-colombus.dtb \ + sun7i-a20-cubieboard2.dtb \ sun7i-a20-olinuxino-micro.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts new file mode 100644 index 0000000..31b76f0 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" + +/ { + model = "Cubietech Cubieboard2"; + compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; + + soc@01c00000 { + pinctrl@01c20800 { + led_pins_cubieboard2: led_pins@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_cubieboard2>; + + blue { + label = "cubieboard2:blue:usr"; + gpios = <&pio 7 21 0>; + }; + + green { + label = "cubieboard2:green:usr"; + gpios = <&pio 7 20 0>; + }; + }; +}; -- cgit v1.1 From adc9afb658d2ff268365a17b60ca54b43429a77d Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Sat, 8 Jun 2013 13:51:04 +0800 Subject: ARM: at91/dt: sama5d3xek: remove the useless NFC dt parameters The NFC driver code doesn't use atmel,has-nfc and atmel,use-nfc-sram. Signed-off-by: Josh Wu --- arch/arm/boot/dts/sama5d3xcm.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 1f80508..31ed9e3 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -47,8 +47,6 @@ atmel,has-pmecc; atmel,pmecc-cap = <4>; atmel,pmecc-sector-size = <512>; - atmel,has-nfc; - atmel,use-nfc-sram; nand-on-flash-bbt; status = "okay"; -- cgit v1.1 From 8ae599ef5867b4b38c6accc33abed78dc4d3f02a Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Wed, 5 Jun 2013 19:17:31 +0800 Subject: ARM: at91/dt: sama5d3xek: Enable NFC support in dts Signed-off-by: Josh Wu --- arch/arm/boot/dts/sama5d3.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index ff63fbb..e994cce 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1034,13 +1034,11 @@ compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; #size-cells = <1>; + ranges; reg = < 0x60000000 0x01000000 /* EBI CS3 */ 0xffffc070 0x00000490 /* SMC PMECC regs */ 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 0x00100000 0x00100000 /* ROM code */ - 0x70000000 0x10000000 /* NFC Command Registers */ - 0xffffc000 0x00000070 /* NFC HSMC regs */ - 0x00200000 0x00100000 /* NFC SRAM banks */ >; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; @@ -1049,6 +1047,17 @@ pinctrl-0 = <&pinctrl_nand0_ale_cle>; atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; status = "disabled"; + + nfc@70000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x70000000 0x10000000 /* NFC Command Registers */ + 0xffffc000 0x00000070 /* NFC HSMC regs */ + 0x00200000 0x00100000 /* NFC SRAM banks */ + >; + }; }; }; }; -- cgit v1.1 From afa6a2a726766d8145dc87f47073c745aa0f0d01 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Fri, 23 Aug 2013 14:27:41 +0800 Subject: ARM: at91/dt: sama5d3xek: reduce the ROM code mapping for pmecc lookup table Signed-off-by: Josh Wu --- arch/arm/boot/dts/sama5d3.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index e994cce..b7f4961 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1038,14 +1038,14 @@ reg = < 0x60000000 0x01000000 /* EBI CS3 */ 0xffffc070 0x00000490 /* SMC PMECC regs */ 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ - 0x00100000 0x00100000 /* ROM code */ + 0x00110000 0x00018000 /* ROM code */ >; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_ale_cle>; - atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; status = "disabled"; nfc@70000000 { -- cgit v1.1 From 24b44d24dc823cc56060bbffd093b08c8f9139c8 Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Mon, 26 Aug 2013 02:28:05 +0900 Subject: ARM: dts: Fix the RTC DT node name for Exynos5250 Fixes the RTC DT node name for Exynos5250 as per the DT node naming convention. Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5.dtsi | 2 +- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- arch/arm/boot/dts/exynos5250-snow.dts | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 6afa57d..074739d 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -95,7 +95,7 @@ interrupts = <0 54 0>; }; - rtc { + rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; interrupts = <0 43 0>, <0 44 0>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 452d0b0..264913f 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -538,7 +538,7 @@ }; }; - rtc { + rtc@101E0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index e79331d..24413a6 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -171,7 +171,7 @@ }; }; - rtc { + rtc@101E0000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 63ef124..320e82d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -180,7 +180,7 @@ clock-names = "mfc"; }; - rtc { + rtc@101E0000 { clocks = <&clock 337>; clock-names = "rtc"; }; -- cgit v1.1 From 73784475febfc69945f4663fc0ba287cdf535460 Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Mon, 26 Aug 2013 02:28:05 +0900 Subject: ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC Moves the RTC DT node's "status" property from exynos5250 board (arndale & snow) dts files to exynos5250.dtsi, since the bindings in exynos5250.dtsi depicts the RTC h/w completely. Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 4 ---- arch/arm/boot/dts/exynos5250-snow.dts | 4 ---- arch/arm/boot/dts/exynos5250.dtsi | 1 + 3 files changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 264913f..cee55fa 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -538,10 +538,6 @@ }; }; - rtc@101E0000 { - status = "okay"; - }; - usb_hub_bus { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 24413a6..fd711e2 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -171,10 +171,6 @@ }; }; - rtc@101E0000 { - status = "okay"; - }; - /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 320e82d..b4740af 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -183,6 +183,7 @@ rtc@101E0000 { clocks = <&clock 337>; clock-names = "rtc"; + status = "okay"; }; tmu@10060000 { -- cgit v1.1 From a81951d965d2f110ca6f30cf514361d723ca981c Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Mon, 26 Aug 2013 02:28:05 +0900 Subject: ARM: dts: Add RTC DT node to Exynos5420 SoC Adds RTC DT node to Exynos5420 SoC Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c950bad..a18f6b0 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -180,6 +180,12 @@ interrupts = <0 47 0>; }; + rtc@101E0000 { + clocks = <&clock 317>; + clock-names = "rtc"; + status = "okay"; + }; + serial@12C00000 { clocks = <&clock 257>, <&clock 128>; clock-names = "uart", "clk_uart_baud0"; -- cgit v1.1 From f408f9db7deb9ce24b4a8875fdf54483d5068627 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Mon, 26 Aug 2013 02:44:30 +0900 Subject: ARM: dts: add ADC device tree node for exynos5420/5250 Add ADC device tree node for exynos5420 and exynos5250 Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 11 +++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 11 +++++++++++ 2 files changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b4740af..b2841e6 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -642,4 +642,15 @@ clocks = <&clock 133>, <&clock 339>; clock-names = "sclk_fimd", "fimd"; }; + + adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v1"; + reg = <0x12D10000 0x100>, <0x10040718 0x4>; + interrupts = <0 106 0>; + clocks = <&clock 303>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index a18f6b0..0646fa7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -224,4 +224,15 @@ clocks = <&clock 147>, <&clock 421>; clock-names = "sclk_fimd", "fimd"; }; + + adc: adc@12D10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12D10000 0x100>, <0x10040720 0x4>; + interrupts = <0 106 0>; + clocks = <&clock 270>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; }; -- cgit v1.1 From 29bb805475effce2522e0ae60fbfbcd135f363e6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Jul 2013 11:28:58 +0200 Subject: ARM: sun5i: dt: Use the A10s gates in the DTSI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A10s has only a subset of the A10 gates. Now that the clock driver has support for this gates set, switch to it in the DTSI. Signed-off-by: Maxime Ripard Tested-by: Emilio López --- arch/arm/boot/dts/sun5i-a10s.dtsi | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index ee0ff9b..3b4a057 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -95,20 +95,16 @@ ahb_gates: ahb_gates@01c20060 { #clock-cells = <1>; - compatible = "allwinner,sun4i-ahb-gates-clk"; + compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; - clock-output-names = "ahb_usb0", "ahb_ehci0", - "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", - "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", - "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", - "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", - "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", - "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", - "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", - "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", - "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", - "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", + "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", + "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", + "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", + "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", + "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", + "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; }; apb0: apb0@01c20054 { @@ -120,12 +116,11 @@ apb0_gates: apb0_gates@01c20068 { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb0-gates-clk"; + compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; - clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", - "apb0_ir1", "apb0_keypad"; + clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", + "apb0_ir", "apb0_keypad"; }; /* dummy is pll62 */ @@ -145,15 +140,12 @@ apb1_gates: apb1_gates@01c2006c { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb1-gates-clk"; + compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_can", "apb1_scr", - "apb1_ps20", "apb1_ps21", "apb1_uart0", - "apb1_uart1", "apb1_uart2", "apb1_uart3", - "apb1_uart4", "apb1_uart5", "apb1_uart6", - "apb1_uart7"; + "apb1_i2c2", "apb1_uart0", "apb1_uart1", + "apb1_uart2", "apb1_uart3"; }; }; -- cgit v1.1 From 98096560ebb84a3bbbc871bb6b67f25565113135 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 23 Jul 2013 23:54:19 +0200 Subject: ARM: sun6i: Enable clock support in the DTSI Now that the clock driver has support for the A31 clocks, we can add them to the DTSI and start using them in the relevant hardware blocks. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 144 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 134 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index dc5da4f..f244f5f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -51,13 +51,137 @@ clocks { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges; - osc: oscillator { + osc24M: osc24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + pll1: pll1@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + }; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + pll6: pll6 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cpu: cpu@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20050 0x4>; + + /* + * PLL1 is listed twice here. + * While it looks suspicious, it's actually documented + * that way both in the datasheet and in the code from + * Allwinner. + */ + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + }; + + axi: axi@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + }; + + ahb1_mux: ahb1_mux@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + }; + + ahb1: ahb1@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1_mux>; + }; + + ahb1_gates: ahb1_gates@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb1>; + clock-output-names = "ahb1_mipidsi", "ahb1_ss", + "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", + "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", + "ahb1_nand0", "ahb1_sdram", + "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", + "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", + "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", + "ahb1_ehci1", "ahb1_ohci0", + "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", + "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", + "ahb1_hdmi", "ahb1_de0", "ahb1_de1", + "ahb1_fe0", "ahb1_fe1", "ahb1_mp", + "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", + "ahb1_drc0", "ahb1_drc1"; + }; + + apb1: apb1@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + }; + + apb1_gates: apb1_gates@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-apb1-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_codec", "apb1_digital_mic", + "apb1_pio", "apb1_daudio0", + "apb1_daudio1"; + }; + + apb2_mux: apb2_mux@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + }; + + apb2: apb2@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-apb2-div-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb2_mux>; + }; + + apb2_gates: apb2_gates@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-apb2-gates-clk"; + reg = <0x01c2006c 0x8>; + clocks = <&apb2>; + clock-output-names = "apb2_i2c0", "apb2_i2c1", + "apb2_i2c2", "apb2_i2c3", "apb2_uart0", + "apb2_uart1", "apb2_uart2", "apb2_uart3", + "apb2_uart4", "apb2_uart5"; + }; }; soc@01c00000 { @@ -70,7 +194,7 @@ compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>; - clocks = <&osc>; + clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; #address-cells = <1>; @@ -93,7 +217,7 @@ <0 20 1>, <0 21 1>, <0 22 1>; - clocks = <&osc>; + clocks = <&osc24M>; }; wdt1: watchdog@01c20ca0 { @@ -107,7 +231,7 @@ interrupts = <0 0 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 16>; status = "disabled"; }; @@ -117,7 +241,7 @@ interrupts = <0 1 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 17>; status = "disabled"; }; @@ -127,7 +251,7 @@ interrupts = <0 2 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 18>; status = "disabled"; }; @@ -137,7 +261,7 @@ interrupts = <0 3 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 19>; status = "disabled"; }; @@ -147,7 +271,7 @@ interrupts = <0 4 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 20>; status = "disabled"; }; @@ -157,7 +281,7 @@ interrupts = <0 5 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb2_gates 21>; status = "disabled"; }; -- cgit v1.1 From de7dc935557b0b5fcfe4a9c4802f51e3e9cb8d45 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 21:12:52 +0200 Subject: ARM: sun7i: Enable the A20 clocks in the DTSI Now that the clock driver knows about the available clocks found on the A20, we can build up the clock tree from the device tree. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 126 +++++++++++++++++++++++++++++++++++---- 1 file changed, 116 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index f4e4524..999ff45 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -44,7 +44,8 @@ osc24M: osc24M@01c20050 { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "allwinner,sun4i-osc-clk"; + reg = <0x01c20050 0x4>; clock-frequency = <24000000>; }; @@ -53,6 +54,111 @@ compatible = "fixed-clock"; clock-frequency = <32768>; }; + + pll1: pll1@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + }; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + pll6: pll6 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + }; + + ahb_gates: ahb_gates@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", + "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", + "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", + "ahb_spi2", "ahb_spi3", "ahb_sata", + "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", + "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", + "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", + "ahb_de_fe1", "ahb_gmac", "ahb_mp", + "ahb_mali"; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + }; + + apb0_gates: apb0_gates@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis0", "apb0_iis1", + "apb0_pio", "apb0_ir0", "apb0_ir1", + "apb0_iis2", "apb0_keypad"; + }; + + apb1_mux: apb1_mux@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6>, <&osc32k>; + }; + + apb1: apb1@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb1_mux>; + }; + + apb1_gates: apb1_gates@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun7i-a20-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_i2c3", "apb1_can", + "apb1_scr", "apb1_ps20", "apb1_ps21", + "apb1_i2c4", "apb1_uart0", "apb1_uart1", + "apb1_uart2", "apb1_uart3", "apb1_uart4", + "apb1_uart5", "apb1_uart6", "apb1_uart7"; + }; }; soc@01c00000 { @@ -65,7 +171,7 @@ compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <0 28 1>; - clocks = <&osc24M>; + clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; #address-cells = <1>; @@ -117,7 +223,7 @@ interrupts = <0 1 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 16>; status = "disabled"; }; @@ -127,7 +233,7 @@ interrupts = <0 2 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 17>; status = "disabled"; }; @@ -137,7 +243,7 @@ interrupts = <0 3 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 18>; status = "disabled"; }; @@ -147,7 +253,7 @@ interrupts = <0 4 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 19>; status = "disabled"; }; @@ -157,7 +263,7 @@ interrupts = <0 17 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 20>; status = "disabled"; }; @@ -167,7 +273,7 @@ interrupts = <0 18 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 21>; status = "disabled"; }; @@ -177,7 +283,7 @@ interrupts = <0 19 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 22>; status = "disabled"; }; @@ -187,7 +293,7 @@ interrupts = <0 20 1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb1_gates 23>; status = "disabled"; }; -- cgit v1.1 From a2bdc32a527e817fdfa6c56eaa6c70f217da6c6c Mon Sep 17 00:00:00 2001 From: "Jon Medhurst (Tixy)" Date: Fri, 30 Aug 2013 15:26:00 +0100 Subject: ARM: dts: vexpress: Add CCI node to TC2 device-tree The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is needed to get Multi-Cluster Power Management (MCPM) working. Signed-off-by: Jon Medhurst Acked-by: Pawel Moll Acked-by: Lorenzo Pieralisi Signed-off-by: Olof Johansson --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index d2803be..12bd4ea 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -37,30 +37,35 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + cci-control-port = <&cci_control1>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + cci-control-port = <&cci_control2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + cci-control-port = <&cci_control2>; }; cpu4: cpu@4 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + cci-control-port = <&cci_control2>; }; }; @@ -104,6 +109,26 @@ interrupts = <1 9 0xf04>; }; + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + memory-controller@7ffd0000 { compatible = "arm,pl354", "arm,primecell"; reg = <0 0x7ffd0000 0 0x1000>; -- cgit v1.1