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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-05-26 14:42:57 +0200 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-06-03 15:17:07 -0700 |
| commit | 4d52b2acefdfceae0e47ed08324a96f511dc80b1 (patch) | |
| tree | 7348889850e9f896bda2842ad0e3c15165832fad /Documentation/devicetree | |
| parent | 5343325ff3dd299f459fa9dacbd95dca5c9bf215 (diff) | |
| download | op-kernel-dev-4d52b2acefdfceae0e47ed08324a96f511dc80b1.zip op-kernel-dev-4d52b2acefdfceae0e47ed08324a96f511dc80b1.tar.gz | |
clk: mvebu: add missing CESA gate clk
Even if not documented in the datasheet, the Armada 370 SoC can actually
gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA
gateclk in the crypto node.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt index 31c7c0c..660e649 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt @@ -19,6 +19,7 @@ ID Clock Peripheral 9 pex1 PCIe Cntrl 1 15 sata0 SATA Host 0 17 sdio SDHCI Host +23 crypto CESA (crypto engine) 25 tdm Time Division Mplx 28 ddr DDR Cntrl 30 sata1 SATA Host 0 |
