summaryrefslogtreecommitdiffstats
path: root/target-sh4/translate.c
Commit message (Expand)AuthorAgeFilesLines
* Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths2008-07-181-6/+5
* Add missing static qualifiers.pbrook2008-06-291-1/+1
* Add instruction counter.pbrook2008-06-291-0/+31
* SH4 MMU improvementsaurel322008-05-091-0/+4
* Factorize code in translate.caurel322008-04-281-0/+7
* Remove osdep.c/qemu-img code duplicationaurel322008-04-111-0/+1
* SH4, fix several instructionsaurel322008-03-111-51/+82
* use the TCG code generatorbellard2008-02-011-40/+10
* SH4 delay slot code update, by Magnus Damm.ths2007-12-021-45/+72
* fixed FPU rounding initbellard2007-11-111-2/+2
* added cpu_model parameter to cpu_init()bellard2007-11-101-1/+1
* Fix rte opcode, by Magnus Damm.ths2007-09-291-1/+1
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-1/+1
* Fix tb->size mishandling, by Daniel Jacobowitz.ths2007-09-111-1/+0
* SH4 mov.b fix, by Vince Weaver.ths2007-08-261-4/+4
* Ignore PR flag in FPSCR when performing fmov, by Magnus Damm.ths2007-06-221-38/+7
* Document FPSCR usage, by Magnus Damm.ths2007-06-221-19/+19
* Use DREG() instead of XREG() wherever possible, by Magnus Damm.ths2007-06-221-8/+8
* Emulate more fpu opcodes, by Magnus Damm.ths2007-06-221-1/+89
* Set FD bit in SR to emulate kernel behaviour, by Magnus Damm.ths2007-06-221-1/+1
* Fix XHACK() macro and use FREG if possible, by Magnus Damm.ths2007-05-131-4/+4
* Fix opcode for sts.l fpul/cpscr, by Magnus Damm.ths2007-04-261-2/+2
* Define gen_intermediate_code_internal as "static inline".ths2007-03-191-2/+3
* SH bugfixes.pbrook2006-06-181-19/+13
* Remove debug output.pbrook2006-06-171-2/+0
* SH usermode fault handling.pbrook2006-06-171-19/+21
* SH4 rts fix.pbrook2006-06-171-1/+3
* sh4 fmov et al instructions (amatus)bellard2006-06-141-37/+187
* sh4 target (Samuel Tardieu)bellard2006-04-271-0/+1073
OpenPOWER on IntegriCloud