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* target-sh4: Split out T from SRAurelien Jarno2015-06-121-1/+1
* target-sh4: use bit number for SR constantsAurelien Jarno2015-06-121-13/+14
* target-sh4: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-251-0/+9
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-8/+11
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-7/+14
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-26/+25
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-4/+9
* cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber2013-07-231-2/+3
* log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber2013-07-091-1/+1
* hw: move headers to include/Paolo Bonzini2013-04-081-1/+1
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-121-4/+8
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-2/+3
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-9/+9
* target-sh4: Don't overuse CPUStateAndreas Färber2012-03-141-14/+14
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-12-051-1/+1
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| * fix spelling in target sub directoryDong Xu Wang2011-12-021-1/+1
* | sh_intc: convert interrupt controller to memory APIBenoît Canet2011-11-241-0/+3
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* Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-071-2/+2
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+0
* target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno2011-03-031-2/+2
* target-sh4: update PTEH upon MMU exceptionAlexandre Courbot2011-01-261-0/+4
* sh4: implement missing mmaped TLB read functionsAurelien Jarno2011-01-261-0/+74
* sh4: implement missing mmaped TLB write functionsAurelien Jarno2011-01-261-1/+61
* target-sh4: fix index of address read error exceptionAlexandre Courbot2011-01-251-1/+1
* target-sh4: fix TLB invalidation codeAlexandre Courbot2011-01-251-2/+2
* target-sh4: correct use of ! and &Aurelien Jarno2011-01-151-2/+2
* target-sh4: improve TLBAurelien Jarno2011-01-101-21/+44
* target-sh4: implement writes to mmaped ITLBAurelien Jarno2011-01-091-0/+19
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-181-3/+3
* Large page TLB flushPaul Brook2010-03-171-1/+2
* Remove cpu_get_phys_page_debug from userspace emulationPaul Brook2010-03-121-5/+0
* Fix incorrect exception_index useBlue Swirl2010-02-141-1/+1
* target-sh4: MMU: separate execute and read/write permissionsAurelien Jarno2010-02-091-21/+6
* target-sh4: MMU: fix store queue addressesAurelien Jarno2010-02-091-1/+1
* target-sh4: MMU: remove dead codeAurelien Jarno2010-02-091-18/+0
* target-sh4: MMU: optimize UTLB accessesAurelien Jarno2010-02-091-24/+14
* target-sh4: MMU: fix ITLB priviledge checkAurelien Jarno2010-02-091-1/+1
* target-sh4: MMU: simplify call to tlb_set_page()Aurelien Jarno2010-02-091-6/+3
* sh7750: handle MMUCR TI bitAurelien Jarno2010-02-091-0/+18
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-3/+3
* Get rid of _t suffixmalc2009-10-011-3/+3
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
* SH: Fix linux-user _is_cached typo.edgar_igl2009-04-031-1/+1
* SH: Add cpu_sh4_is_cached for linux-user.edgar_igl2009-04-031-0/+6
* SH: Improve movca.l/ocbi emulation.edgar_igl2009-04-011-0/+44
* SH4: Fixed last UTLB unused and URB/URC managementaurel322009-03-031-1/+1
* SH4: Fixed last UTLB unusedaurel322009-03-031-1/+1
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