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* target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
* target-mips: Change TODO fileJia Liu2012-10-311-2/+1
* target-mips: Add ASE DSP processorsJia Liu2012-10-311-0/+52
* target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-313-0/+995
* target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-313-0/+635
* target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-313-0/+311
* target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-313-0/+1499
* target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-313-0/+618
* target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-313-3/+1812
* target-mips: Add ASE DSP load instructionsJia Liu2012-10-311-0/+88
* target-mips: Add ASE DSP branch instructionsJia Liu2012-10-311-0/+36
* Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu2012-10-311-27/+95
* target-mips: Add ASE DSP resources access checkJia Liu2012-10-313-2/+47
* target-mips: Add ASE DSP internal functionsJia Liu2012-10-312-1/+1064
* target-mips: Use TCG registers for the FPU.Richard Henderson2012-10-281-42/+54
* target-mips: rename helper flagsAurelien Jarno2012-10-281-53/+53
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-233-18/+18
* target-mips: Pass MIPSCPU to mips_vpe_sleep()Andreas Färber2012-10-171-3/+7
* target-mips: Pass MIPSCPU to mips_tc_sleep()Andreas Färber2012-10-171-3/+5
* target-mips: Pass MIPSCPU to mips_vpe_is_wfi()Andreas Färber2012-10-171-4/+8
* target-mips: Pass MIPSCPU to mips_tc_wake()Andreas Färber2012-10-171-3/+8
* target-mips: Clean up other_cpu in helper_{d,e}vpe()Andreas Färber2012-10-171-14/+14
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+2
* target-mips: Implement Loongson Multimedia InstructionsRichard Henderson2012-09-194-4/+1180
* target-mips: Always evaluate debugging macro argumentsRichard Henderson2012-09-191-14/+17
* target-mips: Fix MIPS_DEBUG.Richard Henderson2012-09-191-36/+38
* target-mips: Set opn in gen_ldst_multiple.Richard Henderson2012-09-191-0/+6
* target-mips: switch to AREG0 free modeBlue Swirl2012-09-155-1085/+1162
* MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki2012-09-083-62/+52
* target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson2012-08-271-1/+9
* target-mips: add privilege level check to several Cop0 instructionsEric Johnson2012-08-271-0/+9
* mips-linux-user: Always support rdhwr.Richard Henderson2012-08-271-0/+4
* target-mips: Streamline indexed cp1 memory addressing.Richard Henderson2012-08-271-2/+1
* Fix order of CVT.PS.S operandsRichard Sandiford2012-08-271-1/+1
* Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford2012-08-271-2/+2
* target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil2012-08-241-46/+29
* target-mips: Enable access to required RDHWR hardware registersMeador Inge2012-08-231-2/+3
* MIPS: Correct FCR0 initializationNathan Froyd2012-08-091-0/+1
* build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini2012-06-071-1/+2
* build: move libobj-y variable to nested Makefile.objsPaolo Bonzini2012-06-071-1/+3
* build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2012-06-071-0/+1
* Kill off cpu_state_reset()Andreas Färber2012-06-041-0/+3
* target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2012-06-042-4/+12
* target-mips: Use cpu_reset() in do_interrupt()Andreas Färber2012-06-041-1/+2
* target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber2012-06-041-1/+1
* mips: Fix BC1ANY[24]F instructionsRichard Sandiford2012-05-191-4/+4
* target-mips: Remove commented-out function declarationAndreas Färber2012-05-121-1/+0
* target-mips: Remove unused inline functionStefan Weil2012-05-031-6/+0
* Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl2012-05-014-2/+148
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| * target-mips: Start QOM'ifying CPU initAndreas Färber2012-04-302-1/+9
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