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* Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.ths2007-05-201-2/+23
* More MIPS 64-bit FPU support.ths2007-05-191-0/+92
* - Move FPU exception handling into helper functions, since they are big.ths2007-05-181-0/+541
* More generic 64 bit multiplication support, by Aurelien Jarno.ths2007-05-161-14/+0
* Full MIPS64 MMU implementation, by Aurelien Jarno.ths2007-05-131-0/+3
* MMU code improvements, by Aurelien Jarno.ths2007-05-131-5/+13
* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-131-43/+21
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-11/+9
* Fix qemu SIGFPE caused by division-by-zero due to underflow.ths2007-04-151-0/+11
* Delete unused define.ths2007-04-151-2/+0
* Nicer Log formatting.ths2007-04-131-1/+1
* Save state for all CP0 instructions, they may throw a CPU exception.ths2007-04-061-11/+27
* Fix rotr immediate ops, mask shift/rotate arguments to their allowedths2007-04-051-4/+2
* Build fix for 64bit machines. (This is still not correct mul/div handling.)ths2007-04-021-6/+12
* Actually enable 64bit configuration.ths2007-04-011-3/+3
* MIPS64 configurations.ths2007-04-011-2/+0
* Sanitize mips exception handling.ths2007-03-301-3/+5
* Fix enough FPU/R2 support to get 24Kf going.ths2007-03-231-2/+7
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-281-2/+0
* Replace TLSZ with TARGET_FMT_lx.ths2007-02-201-3/+3
* Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths2007-02-181-1/+1
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-241-0/+5
* Implementing dmfc/dmtc.ths2007-01-231-6/+6
* Fix PageMask handling, second part.ths2007-01-221-0/+2
* Bring TLB / PageSize handling in line with real hardware behaviour.ths2007-01-211-8/+0
* moved invalidate_tlb() to helper.c as a work around for gcc 3.2.2 bug - suppr...bellard2007-01-031-45/+3
* Simplify code and fix formatting.ths2007-01-011-6/+6
* Scrap SIGN_EXTEND32.ths2006-12-211-6/+6
* Preliminiary MIPS64 support, disabled by default due to performance impact.ths2006-12-211-16/+130
* Add MIPS32R2 instructions, and generally straighten out the instructionths2006-12-061-3/+3
* Dynamically translate MIPS mtc0 instructions.ths2006-12-061-216/+31
* Dynamically translate MIPS mfc0 instructions.ths2006-12-061-143/+15
* MIPS TLB performance improvements, by Daniel Jacobowitz.ths2006-12-061-6/+48
* Avoid redundant TLB flushes (Daniel Jacobowitz).pbrook2006-11-121-0/+9
* consistent update of ERL and EXLbellard2006-06-261-4/+0
* MIPS FPU support (Marius Goeger)bellard2006-06-141-0/+41
* fix wrong bitmasks for CP0_Context and CP0_EntryHi (Thiemo Seufer)bellard2006-05-221-2/+2
* cosmetics (Thiemo Seufer)bellard2006-05-221-10/+7
* removed unnecessary headerbellard2006-04-231-1/+0
* Avoid flushing of global TLB entries for differing ASIDs (Thiemo Seufer).pbrook2006-03-111-2/+3
* e bitfields in mips TLB structures (Thiemo Seufer).pbrook2006-03-111-30/+22
* MIPS fixes (Daniel Jacobowitz)bellard2005-12-051-4/+54
* mips user emulationbellard2005-11-261-0/+33
* correct split between helper.c and op_helper.c - cosmeticsbellard2005-07-041-14/+55
* use MIPS_TLB_NB constant (Ralf Baechle)bellard2005-07-021-5/+7
* use mask in C0_status (Ralf Baechle)bellard2005-07-021-1/+1
* fixed C0 status codes (Ralf Baechle)bellard2005-07-021-3/+3
* soft irq are just irqs (Ralf Baechle)bellard2005-07-021-1/+1
* MIPS target (Jocelyn Mayer)bellard2005-07-021-0/+634
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