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* Full MIPS64 MMU implementation, by Aurelien Jarno.ths2007-05-131-2/+4
* Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths2007-05-131-63/+15
* Delete misleading comment.ths2007-05-131-2/+0
* MMU code improvements, by Aurelien Jarno.ths2007-05-131-1/+1
* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-131-12/+5
* Implemented cabs FP instructions, and improve exception handling forths2007-05-111-0/+97
* Implement FP madd/msub, wire up bc1any[24][ft].ths2007-05-111-0/+55
* Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths2007-05-091-0/+16
* Work around gcc's mips define, spotted by Stefan Weil.ths2007-05-081-12/+12
* MIPS 64-bit FPU support, plus some collateral bugfixes in theths2007-05-071-202/+718
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-2/+2
* Don't use T2 for INS, it conflicts with branch delay slot handling.ths2007-04-151-2/+2
* Fix qemu SIGFPE caused by division-by-zero due to underflow.ths2007-04-151-12/+11
* Restart interrupts after an exception.ths2007-04-141-1/+14
* Another fix for CP0 Cause register handling.ths2007-04-131-1/+1
* More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths2007-04-111-9/+5
* Fix CP0_IntCtl handling.ths2007-04-091-2/+3
* Proper handling of reserved bits in the context register.ths2007-04-091-1/+1
* Mark watchpoint features as unimplemented.ths2007-04-091-3/+8
* Fix exception handling cornercase for rdhwr.ths2007-04-091-26/+4
* Fix ins/ext cornercase.ths2007-04-071-4/+4
* Save state for all CP0 instructions, they may throw a CPU exception.ths2007-04-061-5/+17
* Fix rotr immediate ops, mask shift/rotate arguments to their allowedths2007-04-051-11/+8
* Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths2007-04-051-19/+49
* Actually enable 64bit configuration.ths2007-04-011-5/+5
* Sanitize mips exception handling.ths2007-03-301-24/+27
* Fix enough FPU/R2 support to get 24Kf going.ths2007-03-231-1/+13
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-181-1/+6
* MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths2007-03-021-0/+7
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-281-9/+0
* Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths2007-02-271-1/+1
* Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths2007-02-181-1/+1
* EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths2007-01-241-17/+2
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-241-51/+11
* Implementing dmfc/dmtc.ths2007-01-231-45/+191
* Fix bad data type.ths2007-01-011-1/+1
* Scrap SIGN_EXTEND32.ths2006-12-211-51/+51
* Preliminiary MIPS64 support, disabled by default due to performance impact.ths2006-12-211-89/+407
* Fix build of MIPS target without FPU support.ths2006-12-071-0/+2
* Add MIPS32R2 instructions, and generally straighten out the instructionths2006-12-061-15/+345
* Dynamically translate MIPS mtc0 instructions.ths2006-12-061-2/+178
* Dynamically translate MIPS mfc0 instructions.ths2006-12-061-2/+160
* MIPS FPU fixes (Daniel Jacobowitz).pbrook2006-11-121-1/+1
* compilation fixbellard2006-10-291-2/+1
* add support for cvt.s.d and cvt.d.s (Aurelien Jarno)bellard2006-10-231-0/+12
* consistent update of ERL and EXLbellard2006-06-261-0/+2
* MIPS FPU support (Marius Goeger)bellard2006-06-141-0/+485
* MIPS single stepping fix (Dirk Behme)bellard2006-04-231-1/+1
* Fix overflow conditions for MIPS add / subtract (Stefan Weil)bellard2006-04-231-2/+4
* MIPS fixes (Daniel Jacobowitz)bellard2005-12-051-6/+16
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