hqemu - HQEMU

	Commit message (Expand)	Author	Age	Files	Lines
*	MIPS TLB style selection at runtime, by Herve Poussineau.	ths	2007-05-13	1	-2/+0
*	Kill broken host register definitions, thanks to Paul Brook and Herve	ths	2007-04-29	1	-2/+0
*	Update comment. We can't easily adhere to the architecture spec because	ths	2007-04-19	1	-3/+3
*	Choose number of TLBs at runtime, by Herve Poussineau.	ths	2007-04-17	1	-1/+0
*	Throw RI for invalid MFMC0-class instructions. Introduce optional	ths	2007-04-11	1	-0/+5
*	Actually enable 64bit configuration.	ths	2007-04-01	1	-4/+1
*	Move mips CPU specific initialization to translate_init.c.	ths	2007-03-21	1	-37/+0
*	MIPS -cpu selection support, by Herve Poussineau.	ths	2007-03-18	1	-26/+0
*	MIPS FPU dynamic activation, part 1, by Herve Poussineau.	ths	2007-02-28	1	-9/+4
*	Preliminiary MIPS64 support, disabled by default due to performance impact.	ths	2006-12-21	1	-3/+10
*	Add MIPS32R2 instructions, and generally straighten out the instruction	ths	2006-12-06	1	-16/+34
*	MIPS TLB performance improvements, by Daniel Jacobowitz.	ths	2006-12-06	1	-0/+1
*	mips config fixes (initial patch by Stefan Weil)	bellard	2006-06-14	1	-11/+14
*	MIPS FPU support (Marius Goeger)	bellard	2006-06-14	1	-3/+9
*	MIPS target (Jocelyn Mayer)	bellard	2005-07-02	1	-0/+58