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* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-112-4/+4
* typofixes - v4Veres Lajos2015-09-111-2/+2
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-113-4/+4
* target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias2015-09-081-0/+6
* target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias2015-09-081-4/+4
* target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias2015-09-081-1/+2
* target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin2015-09-083-4/+13
* target-arm: Refactor CPU affinity handlingPavel Fedin2015-09-074-5/+16
* target-arm: Fix arm_excp_unmasked() functionSergey Sorokin2015-09-071-3/+3
* target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin2015-09-071-32/+32
* arm: Remove hw_error() usages.Peter Crosthwaite2015-09-072-3/+3
* arm: cpu: assert() on no-EL2 virt IRQ error condition.Peter Crosthwaite2015-09-071-4/+1
* target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell2015-09-074-2/+31
* target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter blockPeter Maydell2015-09-071-3/+18
* target-arm/arm-semi.c: Implement A64 specific SyncCacheRange callPeter Maydell2015-09-071-0/+10
* target-arm/arm-semi.c: Support widening APIs to 64 bitsPeter Maydell2015-09-072-13/+58
* target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'Peter Maydell2015-09-071-32/+47
* target-arm: Improve semihosting debug printsChristopher Covington2015-09-071-3/+9
* target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdbPeter Maydell2015-09-071-1/+1
* target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell2015-08-251-0/+55
* target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell2015-08-251-0/+76
* target-arm: Implement missing EL2 TLBI operationsPeter Maydell2015-08-251-0/+22
* target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell2015-08-251-43/+129
* target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell2015-08-251-8/+8
* target-arm: Implement AArch32 ATS1H* operationsPeter Maydell2015-08-251-0/+22
* target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell2015-08-251-5/+11
* target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell2015-08-252-0/+11
* target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell2015-08-251-2/+41
* target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell2015-08-251-0/+5
* target-arm: Implement missing ACTLR registersPeter Maydell2015-08-251-6/+15
* target-arm: Implement missing AFSR registersPeter Maydell2015-08-251-0/+24
* target-arm: Implement missing AMAIR registersPeter Maydell2015-08-251-0/+21
* target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell2015-08-251-0/+8
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-242-53/+53
* target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell2015-08-131-0/+27
* target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell2015-08-134-1/+92
* target-arm: Add debug check for mismatched cpreg resetsPeter Maydell2015-08-133-1/+27
* Introduce gic_class_name() instead of repeating conditionPavel Fedin2015-08-131-0/+5
* target-arm: Add the Hypervisor timerEdgar E. Iglesias2015-08-134-1/+73
* target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias2015-08-131-22/+77
* target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias2015-08-131-7/+5
* target-arm: Add CNTHCTL_EL2Edgar E. Iglesias2015-08-132-2/+32
* target-arm: Add CNTVOFF_EL2Edgar E. Iglesias2015-08-132-6/+42
* target-arm: kvm: Differentiate registers based on write-back levelsChristoffer Dall2015-07-216-6/+76
* target-arm: Fix broken SCTLR_EL3 resetPeter Maydell2015-07-151-0/+1
* disas: arm: QOMify target specific disas setupPeter Crosthwaite2015-07-091-0/+35
* cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite2015-07-091-1/+1
* cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite2015-07-091-1/+1
* cpu: Add Error argument to cpu_exec_init()Bharata B Rao2015-07-091-1/+1
* crypto: move built-in AES implementation into crypto/Daniel P. Berrange2015-07-071-1/+1
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