summaryrefslogtreecommitdiffstats
path: root/target-arm
Commit message (Expand)AuthorAgeFilesLines
* target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell2014-07-082-18/+5
* Fix new typos (found by codespell)Stefan Weil2014-06-241-1/+1
* target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar2014-06-194-0/+9
* target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar2014-06-191-0/+4
* target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possiblePranavkumar Sawargaonkar2014-06-192-0/+6
* target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar2014-06-195-12/+44
* target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell2014-06-191-1/+1
* target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell2014-06-191-1/+2
* target-arm: Add ULL suffix to calculation of page sizePeter Maydell2014-06-191-1/+1
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-192-18/+60
* target-arm: Use Common Tables in AES InstructionsTom Musta2014-06-161-75/+4
* target-arm: Delete unused iwmmxt_msadb helperPeter Maydell2014-06-093-13/+0
* target-arm: Fix errors in writes to generic timer control registersPeter Maydell2014-06-091-3/+3
* target-arm: A64: Implement two-register SHA instructionsPeter Maydell2014-06-091-1/+44
* target-arm: A64: Implement 3-register SHA instructionsPeter Maydell2014-06-091-1/+58
* target-arm: A64: Implement AES instructionsPeter Maydell2014-06-091-1/+50
* target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2014-06-092-19/+16
* target-arm: A64: Implement CRC instructionsPeter Maydell2014-06-093-1/+85
* target-arm: VFPv4 implies half-precision extensionPeter Maydell2014-06-092-4/+1
* target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2014-06-092-4/+14
* target-arm: Remove unnecessary setting of feature bitsPeter Maydell2014-06-092-4/+0
* target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell2014-06-091-3/+0
* target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell2014-06-091-1/+1
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-097-33/+60
* target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell2014-06-091-12/+12
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-095-7/+347
* target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell2014-06-091-9/+8
* target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler2014-06-091-14/+14
* target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell2014-06-091-0/+1
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-053-4/+3
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-055-22/+50
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-289-16/+10
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-272-1/+6
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-272-1/+22
* target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias2014-05-271-1/+1
* target-arm: A64: Generalize update_spsel for the various ELsEdgar E. Iglesias2014-05-271-5/+6
* target-arm: A64: Generalize ERET to various ELsEdgar E. Iglesias2014-05-271-5/+6
* target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias2014-05-271-0/+4
* target-arm: A64: Forbid ERET to higher or unimplemented ELsEdgar E. Iglesias2014-05-271-2/+6
* target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
* target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
* target-arm: Add a feature flag for EL3Edgar E. Iglesias2014-05-271-0/+1
* target-arm: Add a feature flag for EL2Edgar E. Iglesias2014-05-271-0/+1
* target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias2014-05-273-2/+17
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-274-6/+12
* target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2014-05-272-4/+4
* target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2014-05-272-4/+4
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-273-5/+5
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-273-8/+8
OpenPOWER on IntegriCloud