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target-arm
/
translate-a64.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
tcg: Add TCG_MAX_INSNS
Richard Henderson
2015-10-07
1
-0
/
+3
*
target-arm: Add condexec state to insn_start
Richard Henderson
2015-10-07
1
-1
/
+1
*
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
2015-10-07
1
-13
/
+13
*
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
2015-10-07
1
-3
/
+3
*
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
2015-10-07
1
-4
/
+1
*
tcg: Rename debug_insn_start to insn_start
Richard Henderson
2015-10-07
1
-1
/
+1
*
target-arm: Use tcg_gen_extrh_i64_i32
Richard Henderson
2015-09-14
1
-25
/
+9
*
target-arm: Recognize ROR
Richard Henderson
2015-09-14
1
-12
/
+21
*
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
Richard Henderson
2015-09-14
1
-1
/
+5
*
target-arm: Recognize UXTB, UXTH, LSR, LSL
Richard Henderson
2015-09-14
1
-0
/
+17
*
target-arm: Recognize SXTB, SXTH, SXTW, ASR
Richard Henderson
2015-09-14
1
-1
/
+23
*
target-arm: Implement fcsel with movcond
Richard Henderson
2015-09-14
1
-28
/
+17
*
target-arm: Implement ccmp branchless
Richard Henderson
2015-09-14
1
-16
/
+58
*
target-arm: Use setcond and movcond for csel
Richard Henderson
2015-09-14
1
-36
/
+49
*
target-arm: Share all common TCG temporaries
Richard Henderson
2015-09-14
1
-22
/
+0
*
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
2015-09-08
1
-1
/
+5
*
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Peter Maydell
2015-09-07
1
-2
/
+22
*
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
2015-08-24
1
-30
/
+30
*
target-arm: Split DISAS_YIELD from DISAS_WFE
Peter Maydell
2015-07-06
1
-0
/
+6
*
disas: Remove uses of CPU env
Peter Crosthwaite
2015-06-22
1
-1
/
+1
*
target-arm: Don't halt on WFI unless we don't have any work
Peter Maydell
2015-05-29
1
-0
/
+4
*
target-arm: Extend FP checks to use an EL
Greg Bellows
2015-05-29
1
-4
/
+4
*
target-arm: Make singlestate TB flags common between AArch32/64
Peter Maydell
2015-05-29
1
-2
/
+2
*
target-arm: Add exception target el infrastructure
Greg Bellows
2015-05-29
1
-12
/
+22
*
tcg: Change translator-side labels to a pointer
Richard Henderson
2015-03-13
1
-13
/
+13
*
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into staging
Peter Maydell
2015-02-13
1
-7
/
+3
|
\
|
*
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
2015-02-12
1
-6
/
+3
|
*
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
2015-02-12
1
-1
/
+0
*
|
target-arm: A64: Avoid signed shifts in disas_ldst_pair()
Peter Maydell
2015-02-13
1
-1
/
+1
*
|
target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr
Peter Maydell
2015-02-13
1
-2
/
+3
*
|
target-arm: A64: Fix handling of rotate in logic_imm_decode_wmask
Peter Maydell
2015-02-13
1
-1
/
+4
*
|
target-arm: A64: Fix shifts into sign bit
Peter Maydell
2015-02-13
1
-3
/
+3
|
/
*
target-arm: Use correct mmu_idx for unprivileged loads and stores
Peter Maydell
2015-02-05
1
-1
/
+18
*
target-arm: Define correct mmu_idx values and pass them in TB flags
Peter Maydell
2015-02-05
1
-2
/
+3
*
target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT
Peter Maydell
2015-02-05
1
-1
/
+1
*
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
2015-01-03
1
-1
/
+1
*
translate: check cflags instead of use_icount global
Paolo Bonzini
2015-01-03
1
-2
/
+2
*
target-arm: A64: remove redundant store
Alex Bennée
2014-11-02
1
-1
/
+0
*
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
2014-10-24
1
-8
/
+8
*
target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers
Peter Maydell
2014-10-24
1
-2
/
+2
*
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
2014-09-29
1
-0
/
+13
*
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
2014-09-29
1
-9
/
+22
*
target-arm: Implement ARMv8 single-step handling for A64 code
Peter Maydell
2014-08-19
1
-5
/
+86
*
target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb
Peter Maydell
2014-08-19
1
-2
/
+3
*
target-arm: Fix return address for A64 BRK instructions
Peter Maydell
2014-08-19
1
-1
/
+1
*
trace: [tcg] Include TCG-tracing header on all targets
Lluís Vilanova
2014-08-12
1
-0
/
+2
*
target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()
Peter Maydell
2014-06-19
1
-1
/
+1
*
target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()
Peter Maydell
2014-06-19
1
-1
/
+2
*
target-arm: A64: Implement two-register SHA instructions
Peter Maydell
2014-06-09
1
-1
/
+44
*
target-arm: A64: Implement 3-register SHA instructions
Peter Maydell
2014-06-09
1
-1
/
+58
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