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* target-arm: Add MDCR_EL2Sergey Fedorov2015-10-161-0/+12
| | | | | | | | | | | | | Add the MDCR_EL2 register. We don't implement any of the debug-related traps this register controls yet, so currently it simply reads back as written. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message; moved non-dummy definition from debug_cp_reginfo to el2_cp_reginfo.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista2015-10-161-2/+23
| | | | | | | | | | | | | Added oslar_write function to OSLAR_EL1 sysreg, using a status variable in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked to the newly added read-only OSLSR_EL1 register. Linux reads from this register during its suspend/resume procedure. Signed-off-by: Davorin Mista <davorin.mista@aggios.com> [PMM: folded a long line and tweaked a comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin2015-10-161-2/+13
| | | | | | | | | | It is incorrect to call arm_el_is_aa64() function for unimplemented EL. This patch fixes several attempts to do so. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: Reworked several of the comments to be more verbose.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-1/+5
| | | | | | | | | | | | | | | | If any store instruction writes the code inside the same TB after this store insn, the execution of the TB must be stopped to execute new code correctly. As described in ARMv8 manual D3.4.6 self-modifying code must do an IC invalidation to be valid, and an ISB after it. So it's enough to end the TB after ISB instruction on the code translation. Also this TB break is necessary to take any pending interrupts immediately after an ISB (as required by ARMv8 ARM D1.14.4). Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: tweaked commit message and comments slightly] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add missing 'static' attributeStefan Weil2015-10-161-1/+1
| | | | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1443213733-9807-1-git-send-email-sw@weilnetz.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: clarify the use of muldiv64()Laurent Vivier2015-09-251-6/+8
| | | | | | | | | | | | | muldiv64() is used to convert microseconds into CPU ticks. But it is not clear and not commented. This patch uses macro to clearly identify what is used: time, CPU frequency and ticks. For an elapsed time and a given frequency, we compute how many ticks we have. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Use new revbit functionsRichard Henderson2015-09-151-11/+1
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Add VMPIDR_EL2Edgar E. Iglesias2015-09-141-2/+24
| | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Break out mpidr_read_val()Edgar E. Iglesias2015-09-141-1/+6
| | | | | | | | | | | | Break out mpidr_read_val() to allow future sharing of the code that conditionally sets the M and U bits of MPIDR. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add VPIDR_EL2Edgar E. Iglesias2015-09-141-1/+41
| | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-7-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias2015-09-141-2/+4
| | | | | | | | | | Stage-2 translations, EL2 and EL3 regimes don't have the EPD control. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-6-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias2015-09-141-1/+3
| | | | | | | | | | Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add VTTBR_EL2Edgar E. Iglesias2015-09-141-2/+32
| | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add VTCR_EL2Edgar E. Iglesias2015-09-141-2/+41
| | | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed typo in comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-2/+2
| | | | | | | | | | | | | | | | | | This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-111-1/+1
| | | | | | | | | | | | Many source files have doubled words (eg "the the", "to to", and so on). Most of these can simply be removed, but a couple were actual mis-spellings (eg "to to" instead of "to do"). There was even one triple word score "to to to" :-) Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias2015-09-081-0/+6
| | | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias2015-09-081-4/+4
| | | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin2015-09-071-32/+32
| | | | | | | | | | | | | There is an error in functions aarch64_sync_32_to_64() and aarch64_sync_64_to_32() with mapping of registers between AArch32 and AArch64. This commit fixes the mapping to match the v8 ARM ARM section D1.20.1 (table D1-77). Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1440796451-15276-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tidied commit message a bit] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Remove hw_error() usages.Peter Crosthwaite2015-09-071-1/+1
| | | | | | | | | | | | All of these hw_errors are fatal and indicate something wrong with QEMU implementation. Convert to g_assert_not_reached. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 169194d09017e5725535d31a1507d454c0043706.1440842587.git.crosthwaite.peter@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Improve semihosting debug printsChristopher Covington2015-09-071-3/+9
| | | | | | | | | | | | | Print semihosting debugging information before the do_arm_semihosting() call so that angel_SWIreason_ReportException, which causes the function to not return, gets the same debug prints as other semihosting calls. Also print out the semihosting call number. Signed-off-by: Christopher Covington <christopher.covington@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Christopher Covington <cov@codeaurora.org> Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
* target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell2015-08-251-0/+55
| | | | | | | | | Implement the AArch64 TLBI operations which take an intermediate physical address and invalidate stage 2 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
* target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell2015-08-251-0/+76
| | | | | | | | | Implement the remaining stage 1 TLB invalidate operations visible from EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
* target-arm: Implement missing EL2 TLBI operationsPeter Maydell2015-08-251-0/+22
| | | | | | | | | Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-5-git-send-email-peter.maydell@linaro.org
* target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell2015-08-251-43/+129
| | | | | | | | | | | | | | | Now we have the ability to flush the TLB only for specific MMU indexes, update the AArch64 TLB maintenance instruction implementations to only flush the parts of the TLB they need to, rather than doing full flushes. We take the opportunity to remove some duplicate functions (the per-asid tlb ops work like the non-per-asid ones because we don't support flushing a TLB only by ASID) and to bring the function names in line with the architectural TLBI operation names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-4-git-send-email-peter.maydell@linaro.org
* target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell2015-08-251-8/+8
| | | | | | | | | Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the whole set of AArch64 TLBI regdefs is arranged in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-3-git-send-email-peter.maydell@linaro.org
* target-arm: Implement AArch32 ATS1H* operationsPeter Maydell2015-08-251-0/+22
| | | | | | | | | Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org
* target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell2015-08-251-5/+11
| | | | | | | | | | | | | | | Apply the correct conditions in the ats_access() function for the ATS12NSO* address translation operations: * succeed at EL2 or EL3 * normal UNDEF trap from NS EL1 * trap to EL3 from S EL1 (only possible if EL3 is AArch64) (This change means they're now available in our EL3-supporting CPUs when they would previously always UNDEF.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
* target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell2015-08-251-2/+41
| | | | | | | | | | | | Wire up the AArch64 EL2 and EL3 address translation operations (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some errors in the ats_write64() function in previously unused code that would have done the wrong kind of lookup for accesses from EL3 when SCR.NS==0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-3-git-send-email-peter.maydell@linaro.org
* target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell2015-08-251-0/+5
| | | | | | | | | | For EL2 stage 1 translations, there is no TTBR1. We were already handling this for 64-bit EL2; add the code to take the 'no TTBR1' code path for 64-bit EL2 as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-2-git-send-email-peter.maydell@linaro.org
* target-arm: Implement missing ACTLR registersPeter Maydell2015-08-251-6/+15
| | | | | | | | | | | | We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
* target-arm: Implement missing AFSR registersPeter Maydell2015-08-251-0/+24
| | | | | | | | | | The AFSR registers are implementation dependent auxiliary fault status registers. We already implemented a RAZ/WI AFSR0_EL1 and AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org
* target-arm: Implement missing AMAIR registersPeter Maydell2015-08-251-0/+21
| | | | | | | | | | The AMAIR registers are for providing auxiliary implementation defined memory attributes. We already implemented a RAZ/WI AMAIR_EL1; add the EL2 and EL3 versions for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-3-git-send-email-peter.maydell@linaro.org
* target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell2015-08-251-0/+8
| | | | | | | | | | Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only two which we had implemented the 32-bit Secure equivalents of but not the 64-bit Secure versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-2-git-send-email-peter.maydell@linaro.org
* target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell2015-08-131-0/+27
| | | | | | | | | | | | | | If EL3 is AArch32, then the secure physical timer is accessed via banking of the registers used for the non-secure physical timer. Implement this banking. Note that the access controls for the AArch32 banked registers remain the same as the physical-timer checks; they are not the same as the controls on the AArch64 secure timer registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell2015-08-131-0/+87
| | | | | | | | | | On CPUs with EL3, there are two physical timers, one for Secure and one for Non-secure. Implement this extra timer and the AArch64 registers which access it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
* target-arm: Add debug check for mismatched cpreg resetsPeter Maydell2015-08-131-1/+1
| | | | | | | | | | | | | | | | | It's easy to accidentally define two cpregs which both try to reset the same underlying state field (for instance a clash between an AArch64 EL3 definition and an AArch32 banked register definition). if the two definitions disagree about the reset value then the result is dependent on which one happened to be reached last in the hashtable enumeration. Add a consistency check to detect and assert in these cases: after reset, we run a second pass where we check that the reset operation doesn't change the value of the register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436797559-20835-1-git-send-email-peter.maydell@linaro.org
* target-arm: Add the Hypervisor timerEdgar E. Iglesias2015-08-131-0/+68
| | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias2015-08-131-22/+77
| | | | | | | | | Prepare for adding the Hypervisor timer, no functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias2015-08-131-7/+5
| | | | | | | | | | | Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add CNTHCTL_EL2Edgar E. Iglesias2015-08-131-2/+31
| | | | | | | | | Adds control for trapping selected timer and counter accesses to EL2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add CNTVOFF_EL2Edgar E. Iglesias2015-08-131-6/+41
| | | | | | | | | Adds support for the virtual timer offset controlled by EL2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix broken SCTLR_EL3 resetPeter Maydell2015-07-151-0/+1
| | | | | | | | | | | | | | | The SCTLR_EL3 cpreg definition was implicitly resetting the register state to 0, which is both wrong and clashes with the reset done via the SCTLR definition (since sctlr[3] is unioned with sctlr_s). This went unnoticed until recently, when an unrelated change (commit a903c449b41f105aa) happened to perturb the order of enumeration through the cpregs hashtable for reset such that the erroneous reset happened after the correct one rather than before it. Fix this by marking SCTLR_EL3 as an alias, so its reset is left up to the AArch32 view. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov2015-07-061-1/+1
| | | | | | | | | | | TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* semihosting: create SemihostingConfig structure and semihost.hLeon Alrae2015-06-191-3/+4
| | | | | | | | | | | | | | | Remove semihosting_enabled and semihosting_target and replace them with SemihostingConfig structure containing equivalent fields. The structure is defined in vl.c where it is actually set. Also introduce separate header file include/exec/semihost.h allowing to access semihosting config related stuff from target specific semihosting code. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434643256-16858-2-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement PMSAv7 MPUPeter Crosthwaite2015-06-191-1/+173
| | | | | | | | | | | Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: dcb03cda6dd754c5cc6a962fa11f25089811e954.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add registers for PMSAv7Peter Crosthwaite2015-06-191-7/+83
| | | | | | | | | | | | | Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/helper.c: define MPUIR registerPeter Crosthwaite2015-06-191-0/+10
| | | | | | | | | | | | | Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 9f248950b803a08c8b3c978931663182f7e882e7.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Do not reset sysregs marked as ALIASSergey Fedorov2015-06-191-19/+9
| | | | | | | | | | | | | | | | | cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1434554713-10220-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: helper: rename get_phys_addr_mpuPeter Crosthwaite2015-06-151-5/+5
| | | | | | | | | This get_phys_addr is really for pmsav5. Rename it accordingly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bf4b019aa87d682a45998105ef8e4d4e97a5e117.1434066412.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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