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-rw-r--r--src/hw/xtensa/Makefile.objs3
-rw-r--r--src/hw/xtensa/bootparam.h49
-rw-r--r--src/hw/xtensa/pic_cpu.c166
-rw-r--r--src/hw/xtensa/sim.c115
-rw-r--r--src/hw/xtensa/xtfpga.c512
5 files changed, 845 insertions, 0 deletions
diff --git a/src/hw/xtensa/Makefile.objs b/src/hw/xtensa/Makefile.objs
new file mode 100644
index 0000000..cb77dc3
--- /dev/null
+++ b/src/hw/xtensa/Makefile.objs
@@ -0,0 +1,3 @@
+obj-y += pic_cpu.o
+obj-y += sim.o
+obj-y += xtfpga.o
diff --git a/src/hw/xtensa/bootparam.h b/src/hw/xtensa/bootparam.h
new file mode 100644
index 0000000..955f4e8
--- /dev/null
+++ b/src/hw/xtensa/bootparam.h
@@ -0,0 +1,49 @@
+#ifndef HW_XTENSA_BOOTPARAM
+#define HW_XTENSA_BOOTPARAM
+
+#define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/
+#define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */
+#define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */
+#define BP_TAG_SERIAL_BAUDRATE 0x1004 /* baud rate of current console. */
+#define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */
+#define BP_TAG_FDT 0x1006 /* flat device tree addr */
+
+#define BP_TAG_FIRST 0x7B0B /* first tag with a version number */
+#define BP_TAG_LAST 0x7E0B /* last tag */
+
+typedef struct BpTag {
+ uint16_t tag;
+ uint16_t size;
+} BpTag;
+
+typedef struct BpMemInfo {
+ uint32_t type;
+ uint32_t start;
+ uint32_t end;
+} BpMemInfo;
+
+#define MEMORY_TYPE_CONVENTIONAL 0x1000
+#define MEMORY_TYPE_NONE 0x2000
+
+static inline size_t get_tag_size(size_t data_size)
+{
+ return data_size + sizeof(BpTag) + 4;
+}
+
+static inline ram_addr_t put_tag(ram_addr_t addr, uint16_t tag,
+ size_t size, const void *data)
+{
+ BpTag bp_tag = {
+ .tag = tswap16(tag),
+ .size = tswap16((size + 3) & ~3),
+ };
+
+ cpu_physical_memory_write(addr, &bp_tag, sizeof(bp_tag));
+ addr += sizeof(bp_tag);
+ cpu_physical_memory_write(addr, data, size);
+ addr += (size + 3) & ~3;
+
+ return addr;
+}
+
+#endif
diff --git a/src/hw/xtensa/pic_cpu.c b/src/hw/xtensa/pic_cpu.c
new file mode 100644
index 0000000..18825d1
--- /dev/null
+++ b/src/hw/xtensa/pic_cpu.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "hw/hw.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+
+void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
+{
+ uint32_t old_ccount = env->sregs[CCOUNT] + 1;
+
+ env->sregs[CCOUNT] += d;
+
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
+ int i;
+ for (i = 0; i < env->config->nccompare; ++i) {
+ if (env->sregs[CCOMPARE + i] - old_ccount < d) {
+ xtensa_timer_irq(env, i, 1);
+ }
+ }
+ }
+}
+
+void check_interrupts(CPUXtensaState *env)
+{
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ int minlevel = xtensa_get_cintlevel(env);
+ uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
+ int level;
+
+ /* If the CPU is halted advance CCOUNT according to the QEMU_CLOCK_VIRTUAL time
+ * elapsed since the moment when it was advanced last time.
+ */
+ if (cs->halted) {
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ xtensa_advance_ccount(env,
+ muldiv64(now - env->halt_clock,
+ env->config->clock_freq_khz, 1000000));
+ env->halt_clock = now;
+ }
+ for (level = env->config->nlevel; level > minlevel; --level) {
+ if (env->config->level_mask[level] & int_set_enabled) {
+ env->pending_irq_level = level;
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ qemu_log_mask(CPU_LOG_INT,
+ "%s level = %d, cintlevel = %d, "
+ "pc = %08x, a0 = %08x, ps = %08x, "
+ "intset = %08x, intenable = %08x, "
+ "ccount = %08x\n",
+ __func__, level, xtensa_get_cintlevel(env),
+ env->pc, env->regs[0], env->sregs[PS],
+ env->sregs[INTSET], env->sregs[INTENABLE],
+ env->sregs[CCOUNT]);
+ return;
+ }
+ }
+ env->pending_irq_level = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+}
+
+static void xtensa_set_irq(void *opaque, int irq, int active)
+{
+ CPUXtensaState *env = opaque;
+
+ if (irq >= env->config->ninterrupt) {
+ qemu_log("%s: bad IRQ %d\n", __func__, irq);
+ } else {
+ uint32_t irq_bit = 1 << irq;
+
+ if (active) {
+ env->sregs[INTSET] |= irq_bit;
+ } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
+ env->sregs[INTSET] &= ~irq_bit;
+ }
+
+ check_interrupts(env);
+ }
+}
+
+void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
+{
+ qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
+}
+
+void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
+{
+ int i;
+ uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
+
+ for (i = 0; i < env->config->nccompare; ++i) {
+ if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
+ wake_ccount - env->sregs[CCOUNT]) {
+ wake_ccount = env->sregs[CCOMPARE + i];
+ }
+ }
+ env->wake_ccount = wake_ccount;
+ timer_mod(env->ccompare_timer, env->halt_clock +
+ muldiv64(wake_ccount - env->sregs[CCOUNT],
+ 1000000, env->config->clock_freq_khz));
+}
+
+static void xtensa_ccompare_cb(void *opaque)
+{
+ XtensaCPU *cpu = opaque;
+ CPUXtensaState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+
+ if (cs->halted) {
+ env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);
+ if (!cpu_has_work(cs)) {
+ env->sregs[CCOUNT] = env->wake_ccount + 1;
+ xtensa_rearm_ccompare_timer(env);
+ }
+ }
+}
+
+void xtensa_irq_init(CPUXtensaState *env)
+{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
+ env->irq_inputs = (void **)qemu_allocate_irqs(
+ xtensa_set_irq, env, env->config->ninterrupt);
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
+ env->config->nccompare > 0) {
+ env->ccompare_timer =
+ timer_new_ns(QEMU_CLOCK_VIRTUAL, &xtensa_ccompare_cb, cpu);
+ }
+}
+
+void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
+{
+ if (extint < env->config->nextint) {
+ unsigned irq = env->config->extint[extint];
+ return env->irq_inputs[irq];
+ } else {
+ qemu_log("%s: trying to acquire invalid external interrupt %d\n",
+ __func__, extint);
+ return NULL;
+ }
+}
diff --git a/src/hw/xtensa/sim.c b/src/hw/xtensa/sim.c
new file mode 100644
index 0000000..6266b8d
--- /dev/null
+++ b/src/hw/xtensa/sim.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "elf.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
+#include "qemu/error-report.h"
+
+static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
+{
+ XtensaCPU *cpu = opaque;
+
+ return cpu_get_phys_page_debug(CPU(cpu), addr);
+}
+
+static void sim_reset(void *opaque)
+{
+ XtensaCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void xtensa_sim_init(MachineState *machine)
+{
+ XtensaCPU *cpu = NULL;
+ CPUXtensaState *env = NULL;
+ MemoryRegion *ram, *rom;
+ ram_addr_t ram_size = machine->ram_size;
+ const char *cpu_model = machine->cpu_model;
+ const char *kernel_filename = machine->kernel_filename;
+ int n;
+
+ if (!cpu_model) {
+ cpu_model = XTENSA_DEFAULT_CPU_MODEL;
+ }
+
+ for (n = 0; n < smp_cpus; n++) {
+ cpu = cpu_xtensa_init(cpu_model);
+ if (cpu == NULL) {
+ error_report("unable to find CPU definition '%s'",
+ cpu_model);
+ exit(EXIT_FAILURE);
+ }
+ env = &cpu->env;
+
+ env->sregs[PRID] = n;
+ qemu_register_reset(sim_reset, cpu);
+ /* Need MMU initialized prior to ELF loading,
+ * so that ELF gets loaded into virtual addresses
+ */
+ sim_reset(cpu);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ rom = g_malloc(sizeof(*rom));
+ memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal);
+ vmstate_register_ram_global(rom);
+ memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
+
+ if (kernel_filename) {
+ uint64_t elf_entry;
+ uint64_t elf_lowaddr;
+#ifdef TARGET_WORDS_BIGENDIAN
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
+ &elf_entry, &elf_lowaddr, NULL, 1, EM_XTENSA, 0);
+#else
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
+ &elf_entry, &elf_lowaddr, NULL, 0, EM_XTENSA, 0);
+#endif
+ if (success > 0) {
+ env->pc = elf_entry;
+ }
+ }
+}
+
+static void xtensa_sim_machine_init(MachineClass *mc)
+{
+ mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")";
+ mc->is_default = true;
+ mc->init = xtensa_sim_init;
+ mc->max_cpus = 4;
+}
+
+DEFINE_MACHINE("sim", xtensa_sim_machine_init)
diff --git a/src/hw/xtensa/xtfpga.c b/src/hw/xtensa/xtfpga.c
new file mode 100644
index 0000000..c1bc5ae
--- /dev/null
+++ b/src/hw/xtensa/xtfpga.c
@@ -0,0 +1,512 @@
+/*
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Open Source and Linux Lab nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sysemu/sysemu.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "elf.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "net/net.h"
+#include "hw/sysbus.h"
+#include "hw/block/flash.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/char.h"
+#include "sysemu/device_tree.h"
+#include "qemu/error-report.h"
+#include "bootparam.h"
+
+typedef struct LxBoardDesc {
+ hwaddr flash_base;
+ size_t flash_size;
+ size_t flash_boot_base;
+ size_t flash_sector_size;
+ size_t sram_size;
+} LxBoardDesc;
+
+typedef struct Lx60FpgaState {
+ MemoryRegion iomem;
+ uint32_t leds;
+ uint32_t switches;
+} Lx60FpgaState;
+
+static void lx60_fpga_reset(void *opaque)
+{
+ Lx60FpgaState *s = opaque;
+
+ s->leds = 0;
+ s->switches = 0;
+}
+
+static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ Lx60FpgaState *s = opaque;
+
+ switch (addr) {
+ case 0x0: /*build date code*/
+ return 0x09272011;
+
+ case 0x4: /*processor clock frequency, Hz*/
+ return 10000000;
+
+ case 0x8: /*LEDs (off = 0, on = 1)*/
+ return s->leds;
+
+ case 0xc: /*DIP switches (off = 0, on = 1)*/
+ return s->switches;
+ }
+ return 0;
+}
+
+static void lx60_fpga_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ Lx60FpgaState *s = opaque;
+
+ switch (addr) {
+ case 0x8: /*LEDs (off = 0, on = 1)*/
+ s->leds = val;
+ break;
+
+ case 0x10: /*board reset*/
+ if (val == 0xdead) {
+ qemu_system_reset_request();
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps lx60_fpga_ops = {
+ .read = lx60_fpga_read,
+ .write = lx60_fpga_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
+ hwaddr base)
+{
+ Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
+
+ memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
+ "lx60.fpga", 0x10000);
+ memory_region_add_subregion(address_space, base, &s->iomem);
+ lx60_fpga_reset(s);
+ qemu_register_reset(lx60_fpga_reset, s);
+ return s;
+}
+
+static void lx60_net_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ hwaddr buffers,
+ qemu_irq irq, NICInfo *nd)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+ MemoryRegion *ram;
+
+ dev = qdev_create(NULL, "open_eth");
+ qdev_set_nic_properties(dev, nd);
+ qdev_init_nofail(dev);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(s, 0, irq);
+ memory_region_add_subregion(address_space, base,
+ sysbus_mmio_get_region(s, 0));
+ memory_region_add_subregion(address_space, descriptors,
+ sysbus_mmio_get_region(s, 1));
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384,
+ &error_fatal);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(address_space, buffers, ram);
+}
+
+static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
+ const LxBoardDesc *board,
+ DriveInfo *dinfo, int be)
+{
+ SysBusDevice *s;
+ DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
+
+ qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_abort);
+ qdev_prop_set_uint32(dev, "num-blocks",
+ board->flash_size / board->flash_sector_size);
+ qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
+ qdev_prop_set_uint8(dev, "width", 4);
+ qdev_prop_set_bit(dev, "big-endian", be);
+ qdev_prop_set_string(dev, "name", "lx60.io.flash");
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ memory_region_add_subregion(address_space, board->flash_base,
+ sysbus_mmio_get_region(s, 0));
+ return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
+}
+
+static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
+{
+ XtensaCPU *cpu = opaque;
+
+ return cpu_get_phys_page_debug(CPU(cpu), addr);
+}
+
+static void lx60_reset(void *opaque)
+{
+ XtensaCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
+static uint64_t lx60_io_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ return 0;
+}
+
+static void lx60_io_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+}
+
+static const MemoryRegionOps lx60_io_ops = {
+ .read = lx60_io_read,
+ .write = lx60_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void lx_init(const LxBoardDesc *board, MachineState *machine)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+ int be = 1;
+#else
+ int be = 0;
+#endif
+ MemoryRegion *system_memory = get_system_memory();
+ XtensaCPU *cpu = NULL;
+ CPUXtensaState *env = NULL;
+ MemoryRegion *ram, *rom, *system_io;
+ DriveInfo *dinfo;
+ pflash_t *flash = NULL;
+ QemuOpts *machine_opts = qemu_get_machine_opts();
+ const char *cpu_model = machine->cpu_model;
+ const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
+ const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
+ const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
+ const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
+ int n;
+
+ if (!cpu_model) {
+ cpu_model = XTENSA_DEFAULT_CPU_MODEL;
+ }
+
+ for (n = 0; n < smp_cpus; n++) {
+ cpu = cpu_xtensa_init(cpu_model);
+ if (cpu == NULL) {
+ error_report("unable to find CPU definition '%s'",
+ cpu_model);
+ exit(EXIT_FAILURE);
+ }
+ env = &cpu->env;
+
+ env->sregs[PRID] = n;
+ qemu_register_reset(lx60_reset, cpu);
+ /* Need MMU initialized prior to ELF loading,
+ * so that ELF gets loaded into virtual addresses
+ */
+ cpu_reset(CPU(cpu));
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
+ &error_fatal);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(system_memory, 0, ram);
+
+ system_io = g_malloc(sizeof(*system_io));
+ memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
+ 224 * 1024 * 1024);
+ memory_region_add_subregion(system_memory, 0xf0000000, system_io);
+ lx60_fpga_init(system_io, 0x0d020000);
+ if (nd_table[0].used) {
+ lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
+ xtensa_get_extint(env, 1), nd_table);
+ }
+
+ if (!serial_hds[0]) {
+ serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
+ }
+
+ serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
+ 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
+
+ dinfo = drive_get(IF_PFLASH, 0, 0);
+ if (dinfo) {
+ flash = xtfpga_flash_init(system_io, board, dinfo, be);
+ }
+
+ /* Use presence of kernel file name as 'boot from SRAM' switch. */
+ if (kernel_filename) {
+ uint32_t entry_point = env->pc;
+ size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
+ uint32_t tagptr = 0xfe000000 + board->sram_size;
+ uint32_t cur_tagptr;
+ BpMemInfo memory_location = {
+ .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
+ .start = tswap32(0),
+ .end = tswap32(machine->ram_size),
+ };
+ uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
+ machine->ram_size : 0x08000000;
+ uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
+
+ rom = g_malloc(sizeof(*rom));
+ memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
+ &error_fatal);
+ vmstate_register_ram_global(rom);
+ memory_region_add_subregion(system_memory, 0xfe000000, rom);
+
+ if (kernel_cmdline) {
+ bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
+ }
+ if (dtb_filename) {
+ bp_size += get_tag_size(sizeof(uint32_t));
+ }
+ if (initrd_filename) {
+ bp_size += get_tag_size(sizeof(BpMemInfo));
+ }
+
+ /* Put kernel bootparameters to the end of that SRAM */
+ tagptr = (tagptr - bp_size) & ~0xff;
+ cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
+ cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
+ sizeof(memory_location), &memory_location);
+
+ if (kernel_cmdline) {
+ cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
+ strlen(kernel_cmdline) + 1, kernel_cmdline);
+ }
+ if (dtb_filename) {
+ int fdt_size;
+ void *fdt = load_device_tree(dtb_filename, &fdt_size);
+ uint32_t dtb_addr = tswap32(cur_lowmem);
+
+ if (!fdt) {
+ error_report("could not load DTB '%s'", dtb_filename);
+ exit(EXIT_FAILURE);
+ }
+
+ cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
+ cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
+ sizeof(dtb_addr), &dtb_addr);
+ cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
+ }
+ if (initrd_filename) {
+ BpMemInfo initrd_location = { 0 };
+ int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
+ lowmem_end - cur_lowmem);
+
+ if (initrd_size < 0) {
+ initrd_size = load_image_targphys(initrd_filename,
+ cur_lowmem,
+ lowmem_end - cur_lowmem);
+ }
+ if (initrd_size < 0) {
+ error_report("could not load initrd '%s'", initrd_filename);
+ exit(EXIT_FAILURE);
+ }
+ initrd_location.start = tswap32(cur_lowmem);
+ initrd_location.end = tswap32(cur_lowmem + initrd_size);
+ cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
+ sizeof(initrd_location), &initrd_location);
+ cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
+ }
+ cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
+ env->regs[2] = tagptr;
+
+ uint64_t elf_entry;
+ uint64_t elf_lowaddr;
+ int success = load_elf(kernel_filename, translate_phys_addr, cpu,
+ &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0);
+ if (success > 0) {
+ entry_point = elf_entry;
+ } else {
+ hwaddr ep;
+ int is_linux;
+ success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
+ translate_phys_addr, cpu);
+ if (success > 0 && is_linux) {
+ entry_point = ep;
+ } else {
+ error_report("could not load kernel '%s'",
+ kernel_filename);
+ exit(EXIT_FAILURE);
+ }
+ }
+ if (entry_point != env->pc) {
+ static const uint8_t jx_a0[] = {
+#ifdef TARGET_WORDS_BIGENDIAN
+ 0x0a, 0, 0,
+#else
+ 0xa0, 0, 0,
+#endif
+ };
+ env->regs[0] = entry_point;
+ cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
+ }
+ } else {
+ if (flash) {
+ MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
+ MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
+
+ memory_region_init_alias(flash_io, NULL, "lx60.flash",
+ flash_mr, board->flash_boot_base,
+ board->flash_size - board->flash_boot_base < 0x02000000 ?
+ board->flash_size - board->flash_boot_base : 0x02000000);
+ memory_region_add_subregion(system_memory, 0xfe000000,
+ flash_io);
+ }
+ }
+}
+
+static void xtensa_lx60_init(MachineState *machine)
+{
+ static const LxBoardDesc lx60_board = {
+ .flash_base = 0x08000000,
+ .flash_size = 0x00400000,
+ .flash_sector_size = 0x10000,
+ .sram_size = 0x20000,
+ };
+ lx_init(&lx60_board, machine);
+}
+
+static void xtensa_lx200_init(MachineState *machine)
+{
+ static const LxBoardDesc lx200_board = {
+ .flash_base = 0x08000000,
+ .flash_size = 0x01000000,
+ .flash_sector_size = 0x20000,
+ .sram_size = 0x2000000,
+ };
+ lx_init(&lx200_board, machine);
+}
+
+static void xtensa_ml605_init(MachineState *machine)
+{
+ static const LxBoardDesc ml605_board = {
+ .flash_base = 0x08000000,
+ .flash_size = 0x01000000,
+ .flash_sector_size = 0x20000,
+ .sram_size = 0x2000000,
+ };
+ lx_init(&ml605_board, machine);
+}
+
+static void xtensa_kc705_init(MachineState *machine)
+{
+ static const LxBoardDesc kc705_board = {
+ .flash_base = 0x00000000,
+ .flash_size = 0x08000000,
+ .flash_boot_base = 0x06000000,
+ .flash_sector_size = 0x20000,
+ .sram_size = 0x2000000,
+ };
+ lx_init(&kc705_board, machine);
+}
+
+static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
+ mc->init = xtensa_lx60_init;
+ mc->max_cpus = 4;
+}
+
+static const TypeInfo xtensa_lx60_type = {
+ .name = MACHINE_TYPE_NAME("lx60"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtensa_lx60_class_init,
+};
+
+static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
+ mc->init = xtensa_lx200_init;
+ mc->max_cpus = 4;
+}
+
+static const TypeInfo xtensa_lx200_type = {
+ .name = MACHINE_TYPE_NAME("lx200"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtensa_lx200_class_init,
+};
+
+static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
+ mc->init = xtensa_ml605_init;
+ mc->max_cpus = 4;
+}
+
+static const TypeInfo xtensa_ml605_type = {
+ .name = MACHINE_TYPE_NAME("ml605"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtensa_ml605_class_init,
+};
+
+static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
+ mc->init = xtensa_kc705_init;
+ mc->max_cpus = 4;
+}
+
+static const TypeInfo xtensa_kc705_type = {
+ .name = MACHINE_TYPE_NAME("kc705"),
+ .parent = TYPE_MACHINE,
+ .class_init = xtensa_kc705_class_init,
+};
+
+static void xtensa_lx_machines_init(void)
+{
+ type_register_static(&xtensa_lx60_type);
+ type_register_static(&xtensa_lx200_type);
+ type_register_static(&xtensa_ml605_type);
+ type_register_static(&xtensa_kc705_type);
+}
+
+machine_init(xtensa_lx_machines_init)
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