diff options
Diffstat (limited to 'src/hw/xtensa/sim.c')
| -rw-r--r-- | src/hw/xtensa/sim.c | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/src/hw/xtensa/sim.c b/src/hw/xtensa/sim.c new file mode 100644 index 0000000..6266b8d --- /dev/null +++ b/src/hw/xtensa/sim.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "elf.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "qemu/error-report.h" + +static uint64_t translate_phys_addr(void *opaque, uint64_t addr) +{ + XtensaCPU *cpu = opaque; + + return cpu_get_phys_page_debug(CPU(cpu), addr); +} + +static void sim_reset(void *opaque) +{ + XtensaCPU *cpu = opaque; + + cpu_reset(CPU(cpu)); +} + +static void xtensa_sim_init(MachineState *machine) +{ + XtensaCPU *cpu = NULL; + CPUXtensaState *env = NULL; + MemoryRegion *ram, *rom; + ram_addr_t ram_size = machine->ram_size; + const char *cpu_model = machine->cpu_model; + const char *kernel_filename = machine->kernel_filename; + int n; + + if (!cpu_model) { + cpu_model = XTENSA_DEFAULT_CPU_MODEL; + } + + for (n = 0; n < smp_cpus; n++) { + cpu = cpu_xtensa_init(cpu_model); + if (cpu == NULL) { + error_report("unable to find CPU definition '%s'", + cpu_model); + exit(EXIT_FAILURE); + } + env = &cpu->env; + + env->sregs[PRID] = n; + qemu_register_reset(sim_reset, cpu); + /* Need MMU initialized prior to ELF loading, + * so that ELF gets loaded into virtual addresses + */ + sim_reset(cpu); + } + + ram = g_malloc(sizeof(*ram)); + memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal); + vmstate_register_ram_global(ram); + memory_region_add_subregion(get_system_memory(), 0, ram); + + rom = g_malloc(sizeof(*rom)); + memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal); + vmstate_register_ram_global(rom); + memory_region_add_subregion(get_system_memory(), 0xfe000000, rom); + + if (kernel_filename) { + uint64_t elf_entry; + uint64_t elf_lowaddr; +#ifdef TARGET_WORDS_BIGENDIAN + int success = load_elf(kernel_filename, translate_phys_addr, cpu, + &elf_entry, &elf_lowaddr, NULL, 1, EM_XTENSA, 0); +#else + int success = load_elf(kernel_filename, translate_phys_addr, cpu, + &elf_entry, &elf_lowaddr, NULL, 0, EM_XTENSA, 0); +#endif + if (success > 0) { + env->pc = elf_entry; + } + } +} + +static void xtensa_sim_machine_init(MachineClass *mc) +{ + mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")"; + mc->is_default = true; + mc->init = xtensa_sim_init; + mc->max_cpus = 4; +} + +DEFINE_MACHINE("sim", xtensa_sim_machine_init) |
