diff options
Diffstat (limited to 'hw/pflash_cfi02.c')
| -rw-r--r-- | hw/pflash_cfi02.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 39337ec..9f94c06 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -56,7 +56,7 @@ do { \ struct pflash_t { BlockDriverState *bs; - target_phys_addr_t base; + hwaddr base; uint32_t sector_len; uint32_t chip_len; int mappings; @@ -89,7 +89,7 @@ struct pflash_t { static void pflash_setup_mappings(pflash_t *pfl) { unsigned i; - target_phys_addr_t size = memory_region_size(&pfl->orig_mem); + hwaddr size = memory_region_size(&pfl->orig_mem); memory_region_init(&pfl->mem, "pflash", pfl->mappings * size); pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); @@ -122,10 +122,10 @@ static void pflash_timer (void *opaque) pfl->cmd = 0; } -static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, +static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, int width, int be) { - target_phys_addr_t boff; + hwaddr boff; uint32_t ret; uint8_t *p; @@ -242,10 +242,10 @@ static void pflash_update(pflash_t *pfl, int offset, } } -static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, +static void pflash_write (pflash_t *pfl, hwaddr offset, uint32_t value, int width, int be) { - target_phys_addr_t boff; + hwaddr boff; uint8_t *p; uint8_t cmd; @@ -477,57 +477,57 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, } -static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readb_be(void *opaque, hwaddr addr) { return pflash_read(opaque, addr, 1, 1); } -static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readb_le(void *opaque, hwaddr addr) { return pflash_read(opaque, addr, 1, 0); } -static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readw_be(void *opaque, hwaddr addr) { pflash_t *pfl = opaque; return pflash_read(pfl, addr, 2, 1); } -static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readw_le(void *opaque, hwaddr addr) { pflash_t *pfl = opaque; return pflash_read(pfl, addr, 2, 0); } -static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readl_be(void *opaque, hwaddr addr) { pflash_t *pfl = opaque; return pflash_read(pfl, addr, 4, 1); } -static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) +static uint32_t pflash_readl_le(void *opaque, hwaddr addr) { pflash_t *pfl = opaque; return pflash_read(pfl, addr, 4, 0); } -static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, +static void pflash_writeb_be(void *opaque, hwaddr addr, uint32_t value) { pflash_write(opaque, addr, value, 1, 1); } -static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, +static void pflash_writeb_le(void *opaque, hwaddr addr, uint32_t value) { pflash_write(opaque, addr, value, 1, 0); } -static void pflash_writew_be(void *opaque, target_phys_addr_t addr, +static void pflash_writew_be(void *opaque, hwaddr addr, uint32_t value) { pflash_t *pfl = opaque; @@ -535,7 +535,7 @@ static void pflash_writew_be(void *opaque, target_phys_addr_t addr, pflash_write(pfl, addr, value, 2, 1); } -static void pflash_writew_le(void *opaque, target_phys_addr_t addr, +static void pflash_writew_le(void *opaque, hwaddr addr, uint32_t value) { pflash_t *pfl = opaque; @@ -543,7 +543,7 @@ static void pflash_writew_le(void *opaque, target_phys_addr_t addr, pflash_write(pfl, addr, value, 2, 0); } -static void pflash_writel_be(void *opaque, target_phys_addr_t addr, +static void pflash_writel_be(void *opaque, hwaddr addr, uint32_t value) { pflash_t *pfl = opaque; @@ -551,7 +551,7 @@ static void pflash_writel_be(void *opaque, target_phys_addr_t addr, pflash_write(pfl, addr, value, 4, 1); } -static void pflash_writel_le(void *opaque, target_phys_addr_t addr, +static void pflash_writel_le(void *opaque, hwaddr addr, uint32_t value) { pflash_t *pfl = opaque; @@ -575,9 +575,9 @@ static const MemoryRegionOps pflash_cfi02_ops_le = { .endianness = DEVICE_NATIVE_ENDIAN, }; -pflash_t *pflash_cfi02_register(target_phys_addr_t base, +pflash_t *pflash_cfi02_register(hwaddr base, DeviceState *qdev, const char *name, - target_phys_addr_t size, + hwaddr size, BlockDriverState *bs, uint32_t sector_len, int nb_blocs, int nb_mappings, int width, uint16_t id0, uint16_t id1, |
