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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-20 15:02:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-20 15:02:07 +0000 |
| commit | 3d2bb5cc81ca52dcff854172625a3bb33987495c (patch) | |
| tree | 464c866b0d1337bb232669cbdb7591880926ff20 /tcg/arm/tcg-target.c | |
| parent | 61e8a923646903d76a6d952019716b417d42eedc (diff) | |
| parent | 6399ab3325b7d4f77441c8a00fa9dae98bb0ac43 (diff) | |
| download | hqemu-3d2bb5cc81ca52dcff854172625a3bb33987495c.zip hqemu-3d2bb5cc81ca52dcff854172625a3bb33987495c.tar.gz | |
Merge remote-tracking branch 'remotes/rth/tcg-next' into staging
* remotes/rth/tcg-next:
tcg/i386: Use SHLX/SHRX/SARX instructions
tcg/i386: Use ANDN instruction
tcg/i386: Add tcg_out_vex_modrm
tcg/i386: Move TCG_CT_CONST_* to tcg-target.c
disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX
tcg/optimize: Add more identity simplifications
tcg/optimize: Optmize ANDC X,Y,Y to MOV X,0
tcg/optimize: Simply some logical ops to NOT
tcg/optimize: Handle known-zeros masks for ANDC
tcg/optimize: add known-zero bits compute for load ops
tcg/optimize: improve known-zero bits for 32-bit ops
tcg/optimize: fix known-zero bits optimization
tcg/optimize: fix known-zero bits for right shift ops
tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1].
TCG: Fix 32-bit host allocation typo
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/arm/tcg-target.c')
| -rw-r--r-- | tcg/arm/tcg-target.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 82658a1..c8884b3 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1866,7 +1866,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) : SHIFT_IMM_LSL(0)); } else { - tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[1], 0x20); + tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20); tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], SHIFT_REG_ROR(TCG_REG_TMP)); } |
