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author | Aurelien Jarno <aurelien@aurel32.net> | 2015-07-27 12:41:45 +0200 |
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committer | Richard Henderson <rth@twiddle.net> | 2015-08-24 11:10:54 -0700 |
commit | 870ad1547ac53bc79c21d86cf453b3b20cc660a2 (patch) | |
tree | 7587d872b3c5096a2a8b7c8dc7a2f27f3c34a396 /tcg/README | |
parent | 8bcb5c8f34f9215d4f88f388c7ff14c9bd5cecd3 (diff) | |
download | hqemu-870ad1547ac53bc79c21d86cf453b3b20cc660a2.zip hqemu-870ad1547ac53bc79c21d86cf453b3b20cc660a2.tar.gz |
tcg: update README about size changing ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/README')
-rw-r--r-- | tcg/README | 18 |
1 files changed, 15 insertions, 3 deletions
@@ -466,13 +466,25 @@ On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it (see add2_i32, sub2_i32, brcond2_i32). +On a 64 bit target, the values are transfered between 32 and 64-bit +registers using the following ops: +- trunc_shr_i64_i32 +- ext_i32_i64 +- extu_i32_i64 + +They ensure that the values are correctly truncated or extended when +moved from a 32-bit to a 64-bit register or vice-versa. Note that the +trunc_shr_i64_i32 is an optional op. It is not necessary to implement +it if all the following conditions are met: +- 64-bit registers can hold 32-bit values +- 32-bit values in a 64-bit register do not need to stay zero or + sign extended +- all 32-bit TCG ops ignore the high part of 64-bit registers + Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. -On a 64 bit target, no assumption is made in TCG about the storage of -the 32 bit values in 64 bit registers. - 4.2) Constraints GCC like constraints are used to define the constraints of every |