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| author | Max Filippov <jcmvbkbc@gmail.com> | 2011-09-06 03:55:45 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-09-10 16:57:39 +0000 |
| commit | 6ad6dbf7916c59b6ae6dfe208dd64e0bf89dbf0a (patch) | |
| tree | 29d3895812cc52290289631b5ec2fa8059d25992 /target-xtensa/cpu.h | |
| parent | 797d780b1375b1af1d7713685589bfdec9908dc3 (diff) | |
| download | hqemu-6ad6dbf7916c59b6ae6dfe208dd64e0bf89dbf0a.zip hqemu-6ad6dbf7916c59b6ae6dfe208dd64e0bf89dbf0a.tar.gz | |
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
| -rw-r--r-- | target-xtensa/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 97badf2..1283fd9 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -110,6 +110,7 @@ enum { LEND = 1, LCOUNT = 2, SAR = 3, + LITBASE = 5, SCOMPARE1 = 12, WINDOW_BASE = 72, WINDOW_START = 73, @@ -274,6 +275,7 @@ static inline int cpu_mmu_index(CPUState *env) #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 +#define XTENSA_TBFLAG_LITBASE 0x8 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -285,6 +287,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, if (env->sregs[PS] & PS_EXCM) { *flags |= XTENSA_TBFLAG_EXCM; } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |= XTENSA_TBFLAG_LITBASE; + } } #include "cpu-all.h" |
