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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-07 19:55:37 +0200
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-05-22 17:02:33 +0200
commite5c96c82bc529674b61eacd221734abc2674e264 (patch)
tree1f868a6fbb25d9bf931752028c2afdac97cb4d8c /target-tricore/tricore-opcodes.h
parentddd8cebe3106bdfb2681d8d283296199fd6c7417 (diff)
downloadhqemu-e5c96c82bc529674b61eacd221734abc2674e264.zip
hqemu-e5c96c82bc529674b61eacd221734abc2674e264.tar.gz
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
This instruction was introduced by the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tricore/tricore-opcodes.h')
-rw-r--r--target-tricore/tricore-opcodes.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 7ad6df9..440c7fe 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1120,6 +1120,7 @@ enum {
OPC2_32_RR_DVINIT_U = 0x0a,
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
+ OPC2_32_RR_CRC32 = 0x03,
};
/* OPCM_32_RR_IDIRECT */
enum {
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