diff options
author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-22 19:14:52 +0000 |
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committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-22 19:14:52 +0000 |
commit | e9ebed4d41fc0630e433a32ecfd1057cae8b10bf (patch) | |
tree | f0b197365516014c503bfd86b4c9c86c0daa6777 /target-sparc | |
parent | 3d834c78b28ec08f857ce1fcbd2e962ad7b87740 (diff) | |
download | hqemu-e9ebed4d41fc0630e433a32ecfd1057cae8b10bf.zip hqemu-e9ebed4d41fc0630e433a32ecfd1057cae8b10bf.tar.gz |
Sparc64 update: more VIS ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2714 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r-- | target-sparc/cpu.h | 3 | ||||
-rw-r--r-- | target-sparc/op.c | 467 | ||||
-rw-r--r-- | target-sparc/translate.c | 450 |
3 files changed, 884 insertions, 36 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 50e162a..f3f872f 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -225,6 +225,9 @@ typedef struct CPUSPARCState { uint64_t fprs; uint64_t tick_cmpr, stick_cmpr; uint64_t gsr; + uint32_t gl; // UA2005 + /* UA 2005 hyperprivileged registers */ + uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr; #endif #if !defined(TARGET_SPARC64) && !defined(reg_T2) target_ulong t2; diff --git a/target-sparc/op.c b/target-sparc/op.c index 2c21b53..7a4bd79 100644 --- a/target-sparc/op.c +++ b/target-sparc/op.c @@ -1095,7 +1095,7 @@ void OPPROTO op_rdtick(void) void OPPROTO op_wrtick(void) { - // XXX write cycle counter and bit 31 + T0 = 0; // XXX write cycle counter and bit 31 } void OPPROTO op_rdtpc(void) @@ -1818,8 +1818,7 @@ void OPPROTO op_retry(void) void OPPROTO op_sir(void) { - // XXX - + T0 = 0; // XXX } void OPPROTO op_ld_asi_reg() @@ -1846,6 +1845,44 @@ void OPPROTO op_st_asi() } #ifdef TARGET_SPARC64 +// This function uses non-native bit order +#define GET_FIELD(X, FROM, TO) \ + ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) + +// This function uses the order in the manuals, i.e. bit 0 is 2^0 +#define GET_FIELD_SP(X, FROM, TO) \ + GET_FIELD(X, 63 - (TO), 63 - (FROM)) + +void OPPROTO op_array8() +{ + T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12); +} + +void OPPROTO op_array16() +{ + T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1; +} + +void OPPROTO op_array32() +{ + T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) | + (GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) | + (GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) | + (GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) | + (GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) | + (GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2; +} + void OPPROTO op_alignaddr() { uint64_t tmp; @@ -1862,26 +1899,440 @@ void OPPROTO op_faligndata() tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); - (*((uint64_t *)&DT0)) = tmp; + *((uint64_t *)&DT0) = tmp; } void OPPROTO op_movl_FT0_0(void) { - (*((uint32_t *)&FT0)) = 0; + *((uint32_t *)&FT0) = 0; } void OPPROTO op_movl_DT0_0(void) { - (*((uint64_t *)&DT0)) = 0; + *((uint64_t *)&DT0) = 0; } void OPPROTO op_movl_FT0_1(void) { - (*((uint32_t *)&FT0)) = 0xffffffff; + *((uint32_t *)&FT0) = 0xffffffff; } void OPPROTO op_movl_DT0_1(void) { - (*((uint64_t *)&DT0)) = 0xffffffffffffffffULL; + *((uint64_t *)&DT0) = 0xffffffffffffffffULL; +} + +void OPPROTO op_fnot(void) +{ + *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; +} + +void OPPROTO op_fnots(void) +{ + *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1; +} + +void OPPROTO op_fnor(void) +{ + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); +} + +void OPPROTO op_fnors(void) +{ + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1); +} + +void OPPROTO op_for(void) +{ + *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; +} + +void OPPROTO op_fors(void) +{ + *(uint32_t *)&FT0 |= *(uint32_t *)&FT1; +} + +void OPPROTO op_fxor(void) +{ + *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; +} + +void OPPROTO op_fxors(void) +{ + *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1; +} + +void OPPROTO op_fand(void) +{ + *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; +} + +void OPPROTO op_fands(void) +{ + *(uint32_t *)&FT0 &= *(uint32_t *)&FT1; +} + +void OPPROTO op_fornot(void) +{ + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; +} + +void OPPROTO op_fornots(void) +{ + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1; +} + +void OPPROTO op_fandnot(void) +{ + *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; +} + +void OPPROTO op_fandnots(void) +{ + *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1; +} + +void OPPROTO op_fnand(void) +{ + *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); +} + +void OPPROTO op_fnands(void) +{ + *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1); +} + +void OPPROTO op_fxnor(void) +{ + *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; +} + +void OPPROTO op_fxnors(void) +{ + *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1; +} + +#ifdef WORDS_BIGENDIAN +#define VIS_B64(n) b[7 - (n)] +#define VIS_W64(n) w[3 - (n)] +#define VIS_SW64(n) sw[3 - (n)] +#define VIS_L64(n) l[1 - (n)] +#define VIS_B32(n) b[3 - (n)] +#define VIS_W32(n) w[1 - (n)] +#else +#define VIS_B64(n) b[n] +#define VIS_W64(n) w[n] +#define VIS_SW64(n) sw[n] +#define VIS_L64(n) l[n] +#define VIS_B32(n) b[n] +#define VIS_W32(n) w[n] +#endif + +typedef union { + uint8_t b[8]; + uint16_t w[4]; + int16_t sw[4]; + uint32_t l[2]; + float64 d; +} vis64; + +typedef union { + uint8_t b[4]; + uint16_t w[2]; + uint32_t l; + float32 f; +} vis32; + +void OPPROTO op_fpmerge(void) +{ + vis64 s, d; + + s.d = DT0; + d.d = DT1; + + // Reverse calculation order to handle overlap + d.VIS_B64(7) = s.VIS_B64(3); + d.VIS_B64(6) = d.VIS_B64(3); + d.VIS_B64(5) = s.VIS_B64(2); + d.VIS_B64(4) = d.VIS_B64(2); + d.VIS_B64(3) = s.VIS_B64(1); + d.VIS_B64(2) = d.VIS_B64(1); + d.VIS_B64(1) = s.VIS_B64(0); + //d.VIS_B64(0) = d.VIS_B64(0); + + DT0 = d.d; +} + +void OPPROTO op_fmul8x16(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_W64(r) = tmp >> 8; + + PMUL(0); + PMUL(1); + PMUL(2); + PMUL(3); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fmul8x16al(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_W64(r) = tmp >> 8; + + PMUL(0); + PMUL(1); + PMUL(2); + PMUL(3); +#undef PMUL + + DT0 = d.d; } + +void OPPROTO op_fmul8x16au(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_W64(r) = tmp >> 8; + + PMUL(0); + PMUL(1); + PMUL(2); + PMUL(3); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fmul8sux16(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_W64(r) = tmp >> 8; + + PMUL(0); + PMUL(1); + PMUL(2); + PMUL(3); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fmul8ulx16(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_W64(r) = tmp >> 8; + + PMUL(0); + PMUL(1); + PMUL(2); + PMUL(3); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fmuld8sux16(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_L64(r) = tmp; + + // Reverse calculation order to handle overlap + PMUL(1); + PMUL(0); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fmuld8ulx16(void) +{ + vis64 s, d; + uint32_t tmp; + + s.d = DT0; + d.d = DT1; + +#define PMUL(r) \ + tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ + if ((tmp & 0xff) > 0x7f) \ + tmp += 0x100; \ + d.VIS_L64(r) = tmp; + + // Reverse calculation order to handle overlap + PMUL(1); + PMUL(0); +#undef PMUL + + DT0 = d.d; +} + +void OPPROTO op_fexpand(void) +{ + vis32 s; + vis64 d; + + s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff); + d.d = DT1; + d.VIS_L64(0) = s.VIS_W32(0) << 4; + d.VIS_L64(1) = s.VIS_W32(1) << 4; + d.VIS_L64(2) = s.VIS_W32(2) << 4; + d.VIS_L64(3) = s.VIS_W32(3) << 4; + + DT0 = d.d; +} + +#define VIS_OP(name, F) \ + void OPPROTO name##16(void) \ + { \ + vis64 s, d; \ + \ + s.d = DT0; \ + d.d = DT1; \ + \ + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ + d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ + d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ + d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ + \ + DT0 = d.d; \ + } \ + \ + void OPPROTO name##16s(void) \ + { \ + vis32 s, d; \ + \ + s.f = FT0; \ + d.f = FT1; \ + \ + d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ + d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ + \ + FT0 = d.f; \ + } \ + \ + void OPPROTO name##32(void) \ + { \ + vis64 s, d; \ + \ + s.d = DT0; \ + d.d = DT1; \ + \ + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ + d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ + \ + DT0 = d.d; \ + } \ + \ + void OPPROTO name##32s(void) \ + { \ + vis32 s, d; \ + \ + s.f = FT0; \ + d.f = FT1; \ + \ + d.l = F(d.l, s.l); \ + \ + FT0 = d.f; \ + } + +#define FADD(a, b) ((a) + (b)) +#define FSUB(a, b) ((a) - (b)) +VIS_OP(op_fpadd, FADD) +VIS_OP(op_fpsub, FSUB) + +#define VIS_CMPOP(name, F) \ + void OPPROTO name##16(void) \ + { \ + vis64 s, d; \ + \ + s.d = DT0; \ + d.d = DT1; \ + \ + d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ + d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ + d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ + d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ + \ + DT0 = d.d; \ + } \ + \ + void OPPROTO name##32(void) \ + { \ + vis64 s, d; \ + \ + s.d = DT0; \ + d.d = DT1; \ + \ + d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ + d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ + \ + DT0 = d.d; \ + } + +#define FCMPGT(a, b) ((a) > (b)) +#define FCMPEQ(a, b) ((a) == (b)) +#define FCMPLE(a, b) ((a) <= (b)) +#define FCMPNE(a, b) ((a) != (b)) + +VIS_CMPOP(op_fcmpgt, FCMPGT) +VIS_CMPOP(op_fcmpeq, FCMPEQ) +VIS_CMPOP(op_fcmple, FCMPLE) +VIS_CMPOP(op_fcmpne, FCMPNE) + #endif diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 5a5868f..0812e95 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -350,6 +350,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); // 'a' versions allowed to user depending on asi #if defined(CONFIG_USER_ONLY) #define supervisor(dc) 0 +#define hypervisor(dc) 0 #define gen_op_ldst(name) gen_op_##name##_raw() #define OP_LD_TABLE(width) \ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ @@ -405,6 +406,7 @@ GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); } #define supervisor(dc) (dc->mem_idx == 1) +#define hypervisor(dc) (dc->mem_idx == 2) #endif #else #if defined(CONFIG_USER_ONLY) @@ -1218,14 +1220,40 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; } #if !defined(CONFIG_USER_ONLY) + } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ #ifndef TARGET_SPARC64 - } else if (xop == 0x29) { /* rdpsr / V9 unimp */ if (!supervisor(dc)) goto priv_insn; gen_op_rdpsr(); +#else + if (!hypervisor(dc)) + goto priv_insn; + rs1 = GET_FIELD(insn, 13, 17); + switch (rs1) { + case 0: // hpstate + // gen_op_rdhpstate(); + break; + case 1: // htstate + // gen_op_rdhtstate(); + break; + case 3: // hintp + gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); + break; + case 5: // htba + gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); + break; + case 6: // hver + gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); + break; + case 31: // hstick_cmpr + gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); + break; + default: + goto illegal_insn; + } +#endif gen_movl_T0_reg(rd); break; -#endif } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) goto priv_insn; @@ -1277,6 +1305,14 @@ static void disas_sparc_insn(DisasContext * dc) case 14: // wstate gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); break; + case 16: // UA2005 gl + gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); + break; + case 26: // UA2005 strand status + if (!hypervisor(dc)) + goto priv_insn; + gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); + break; case 31: // ver gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); break; @@ -1997,6 +2033,11 @@ static void disas_sparc_insn(DisasContext * dc) case 1: gen_op_restored(); break; + case 2: /* UA2005 allclean */ + case 3: /* UA2005 otherw */ + case 4: /* UA2005 normalw */ + case 5: /* UA2005 invalw */ + // XXX default: goto illegal_insn; } @@ -2068,6 +2109,14 @@ static void disas_sparc_insn(DisasContext * dc) case 14: // wstate gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); break; + case 16: // UA2005 gl + gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); + break; + case 26: // UA2005 strand status + if (!hypervisor(dc)) + goto priv_insn; + gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); + break; default: goto illegal_insn; } @@ -2076,17 +2125,46 @@ static void disas_sparc_insn(DisasContext * dc) #endif } break; -#ifndef TARGET_SPARC64 - case 0x33: /* wrtbr, V9 unimp */ + case 0x33: /* wrtbr, UA2005 wrhpr */ { +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); - gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); + gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); +#else + if (!hypervisor(dc)) + goto priv_insn; + gen_op_xor_T1_T0(); + switch (rd) { + case 0: // hpstate + // XXX gen_op_wrhpstate(); + save_state(dc); + gen_op_next_insn(); + gen_op_movl_T0_0(); + gen_op_exit_tb(); + dc->is_br = 1; + break; + case 1: // htstate + // XXX gen_op_wrhtstate(); + break; + case 3: // hintp + gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); + break; + case 5: // htba + gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); + break; + case 31: // hstick_cmpr + gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); + break; + case 6: // hver readonly + default: + goto illegal_insn; + } +#endif } break; #endif -#endif #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ { @@ -2164,77 +2242,393 @@ static void disas_sparc_insn(DisasContext * dc) int opf = GET_FIELD_SP(insn, 5, 13); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); + if (gen_trap_ifnofpu(dc)) + goto jmp_insn; switch (opf) { + case 0x000: /* VIS I edge8cc */ + case 0x001: /* VIS II edge8n */ + case 0x002: /* VIS I edge8lcc */ + case 0x003: /* VIS II edge8ln */ + case 0x004: /* VIS I edge16cc */ + case 0x005: /* VIS II edge16n */ + case 0x006: /* VIS I edge16lcc */ + case 0x007: /* VIS II edge16ln */ + case 0x008: /* VIS I edge32cc */ + case 0x009: /* VIS II edge32n */ + case 0x00a: /* VIS I edge32lcc */ + case 0x00b: /* VIS II edge32ln */ + // XXX + goto illegal_insn; + case 0x010: /* VIS I array8 */ + gen_movl_reg_T0(rs1); + gen_movl_reg_T1(rs2); + gen_op_array8(); + gen_movl_T0_reg(rd); + break; + case 0x012: /* VIS I array16 */ + gen_movl_reg_T0(rs1); + gen_movl_reg_T1(rs2); + gen_op_array16(); + gen_movl_T0_reg(rd); + break; + case 0x014: /* VIS I array32 */ + gen_movl_reg_T0(rs1); + gen_movl_reg_T1(rs2); + gen_op_array32(); + gen_movl_T0_reg(rd); + break; case 0x018: /* VIS I alignaddr */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_movl_reg_T0(rs1); gen_movl_reg_T1(rs2); gen_op_alignaddr(); gen_movl_T0_reg(rd); break; + case 0x019: /* VIS II bmask */ case 0x01a: /* VIS I alignaddrl */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; // XXX + goto illegal_insn; + case 0x020: /* VIS I fcmple16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmple16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x022: /* VIS I fcmpne16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpne16(); + gen_op_store_DT0_fpr(rd); break; + case 0x024: /* VIS I fcmple32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmple32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x026: /* VIS I fcmpne32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpne32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x028: /* VIS I fcmpgt16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpgt16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x02a: /* VIS I fcmpeq16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpeq16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x02c: /* VIS I fcmpgt32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpgt32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x02e: /* VIS I fcmpeq32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fcmpeq32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x031: /* VIS I fmul8x16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmul8x16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x033: /* VIS I fmul8x16au */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmul8x16au(); + gen_op_store_DT0_fpr(rd); + break; + case 0x035: /* VIS I fmul8x16al */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmul8x16al(); + gen_op_store_DT0_fpr(rd); + break; + case 0x036: /* VIS I fmul8sux16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmul8sux16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x037: /* VIS I fmul8ulx16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmul8ulx16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x038: /* VIS I fmuld8sux16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmuld8sux16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x039: /* VIS I fmuld8ulx16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fmuld8ulx16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x03a: /* VIS I fpack32 */ + case 0x03b: /* VIS I fpack16 */ + case 0x03d: /* VIS I fpackfix */ + case 0x03e: /* VIS I pdist */ + // XXX + goto illegal_insn; case 0x048: /* VIS I faligndata */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_load_fpr_DT0(rs1); gen_op_load_fpr_DT1(rs2); gen_op_faligndata(); gen_op_store_DT0_fpr(rd); break; + case 0x04b: /* VIS I fpmerge */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fpmerge(); + gen_op_store_DT0_fpr(rd); + break; + case 0x04c: /* VIS II bshuffle */ + // XXX + goto illegal_insn; + case 0x04d: /* VIS I fexpand */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fexpand(); + gen_op_store_DT0_fpr(rd); + break; + case 0x050: /* VIS I fpadd16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fpadd16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x051: /* VIS I fpadd16s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fpadd16s(); + gen_op_store_FT0_fpr(rd); + break; + case 0x052: /* VIS I fpadd32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fpadd32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x053: /* VIS I fpadd32s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fpadd32s(); + gen_op_store_FT0_fpr(rd); + break; + case 0x054: /* VIS I fpsub16 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fpsub16(); + gen_op_store_DT0_fpr(rd); + break; + case 0x055: /* VIS I fpsub16s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fpsub16s(); + gen_op_store_FT0_fpr(rd); + break; + case 0x056: /* VIS I fpsub32 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fpadd32(); + gen_op_store_DT0_fpr(rd); + break; + case 0x057: /* VIS I fpsub32s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fpsub32s(); + gen_op_store_FT0_fpr(rd); + break; case 0x060: /* VIS I fzero */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_movl_DT0_0(); gen_op_store_DT0_fpr(rd); break; case 0x061: /* VIS I fzeros */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_movl_FT0_0(); gen_op_store_FT0_fpr(rd); break; + case 0x062: /* VIS I fnor */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fnor(); + gen_op_store_DT0_fpr(rd); + break; + case 0x063: /* VIS I fnors */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fnors(); + gen_op_store_FT0_fpr(rd); + break; + case 0x064: /* VIS I fandnot2 */ + gen_op_load_fpr_DT1(rs1); + gen_op_load_fpr_DT0(rs2); + gen_op_fandnot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x065: /* VIS I fandnot2s */ + gen_op_load_fpr_FT1(rs1); + gen_op_load_fpr_FT0(rs2); + gen_op_fandnots(); + gen_op_store_FT0_fpr(rd); + break; + case 0x066: /* VIS I fnot2 */ + gen_op_load_fpr_DT1(rs2); + gen_op_fnot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x067: /* VIS I fnot2s */ + gen_op_load_fpr_FT1(rs2); + gen_op_fnot(); + gen_op_store_FT0_fpr(rd); + break; + case 0x068: /* VIS I fandnot1 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fandnot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x069: /* VIS I fandnot1s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fandnots(); + gen_op_store_FT0_fpr(rd); + break; + case 0x06a: /* VIS I fnot1 */ + gen_op_load_fpr_DT1(rs1); + gen_op_fnot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x06b: /* VIS I fnot1s */ + gen_op_load_fpr_FT1(rs1); + gen_op_fnot(); + gen_op_store_FT0_fpr(rd); + break; + case 0x06c: /* VIS I fxor */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fxor(); + gen_op_store_DT0_fpr(rd); + break; + case 0x06d: /* VIS I fxors */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fxors(); + gen_op_store_FT0_fpr(rd); + break; + case 0x06e: /* VIS I fnand */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fnand(); + gen_op_store_DT0_fpr(rd); + break; + case 0x06f: /* VIS I fnands */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fnands(); + gen_op_store_FT0_fpr(rd); + break; + case 0x070: /* VIS I fand */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fand(); + gen_op_store_DT0_fpr(rd); + break; + case 0x071: /* VIS I fands */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fands(); + gen_op_store_FT0_fpr(rd); + break; + case 0x072: /* VIS I fxnor */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fxnor(); + gen_op_store_DT0_fpr(rd); + break; + case 0x073: /* VIS I fxnors */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fxnors(); + gen_op_store_FT0_fpr(rd); + break; case 0x074: /* VIS I fsrc1 */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_load_fpr_DT0(rs1); gen_op_store_DT0_fpr(rd); break; case 0x075: /* VIS I fsrc1s */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_load_fpr_FT0(rs1); gen_op_store_FT0_fpr(rd); break; + case 0x076: /* VIS I fornot2 */ + gen_op_load_fpr_DT1(rs1); + gen_op_load_fpr_DT0(rs2); + gen_op_fornot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x077: /* VIS I fornot2s */ + gen_op_load_fpr_FT1(rs1); + gen_op_load_fpr_FT0(rs2); + gen_op_fornots(); + gen_op_store_FT0_fpr(rd); + break; case 0x078: /* VIS I fsrc2 */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_load_fpr_DT0(rs2); gen_op_store_DT0_fpr(rd); break; case 0x079: /* VIS I fsrc2s */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_load_fpr_FT0(rs2); gen_op_store_FT0_fpr(rd); break; + case 0x07a: /* VIS I fornot1 */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_fornot(); + gen_op_store_DT0_fpr(rd); + break; + case 0x07b: /* VIS I fornot1s */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fornots(); + gen_op_store_FT0_fpr(rd); + break; + case 0x07c: /* VIS I for */ + gen_op_load_fpr_DT0(rs1); + gen_op_load_fpr_DT1(rs2); + gen_op_for(); + gen_op_store_DT0_fpr(rd); + break; + case 0x07d: /* VIS I fors */ + gen_op_load_fpr_FT0(rs1); + gen_op_load_fpr_FT1(rs2); + gen_op_fors(); + gen_op_store_FT0_fpr(rd); + break; case 0x07e: /* VIS I fone */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_movl_DT0_1(); gen_op_store_DT0_fpr(rd); break; case 0x07f: /* VIS I fones */ - if (gen_trap_ifnofpu(dc)) - goto jmp_insn; gen_op_movl_FT0_1(); gen_op_store_FT0_fpr(rd); break; + case 0x080: /* VIS I shutdown */ + case 0x081: /* VIS II siam */ + // XXX + goto illegal_insn; default: goto illegal_insn; } |