diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-13 20:17:54 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-13 20:17:54 +0000 |
| commit | e58c8ba5f6b1bd9af00cf5fcebce4bdba0f0aabb (patch) | |
| tree | c60c6d3fdd9be0629a2bdea913b8f8905c5179bd /target-mips | |
| parent | 5425a2164c99de50ac79e29cdd2cafbc3aafd2f4 (diff) | |
| download | hqemu-e58c8ba5f6b1bd9af00cf5fcebce4bdba0f0aabb.zip hqemu-e58c8ba5f6b1bd9af00cf5fcebce4bdba0f0aabb.tar.gz | |
Another fix for CP0 Cause register handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/helper.c | 2 | ||||
| -rw-r--r-- | target-mips/op.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index c23e9c6..71a9723 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -403,7 +403,7 @@ void do_interrupt (CPUState *env) env->PC = (int32_t)(env->CP0_EBase & ~0x3ff); } env->PC += offset; - env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: if (logfile) { diff --git a/target-mips/op.c b/target-mips/op.c index 9818847..3951204 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1401,7 +1401,7 @@ void op_mtc0_cause (void) if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) mask |= 1 << CP0Ca_DC; - env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask); + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); /* Handle the software interrupt as an hardware one, as they are very similar */ |
