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authorLeon Alrae <leon.alrae@imgtec.com>2013-08-06 11:59:25 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-08-06 13:09:14 +0200
commita1fc6246b3964e74ddb3a7e0b8bba03af1c6ac38 (patch)
treed37b9c5edf885dfad04a4a878412cf52eeb8d17b /target-mips
parent79761c6681f0d1cc1c027116fcb4382d41ed3ece (diff)
downloadhqemu-a1fc6246b3964e74ddb3a7e0b8bba03af1c6ac38.zip
hqemu-a1fc6246b3964e74ddb3a7e0b8bba03af1c6ac38.tar.gz
target-mips: fix decoding of microMIPS POOL32Axf instructions
Fix incorrect assumption that DSP and non-DSP versions of the following instructions have the same encoding: MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO. Correct the existing (non-DSP) instructions and add DSP equivalents. Reference: MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set MIPS Architecture for Programmers Volume IV-e: The MIPS DSP Module for the microMIPS32 Architecture Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c60
1 files changed, 54 insertions, 6 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c1d57a7..e2eb908 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -11061,6 +11061,36 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
}
break;
#endif
+ case 0x2a:
+ switch (minor & 3) {
+ case MADD_ACC:
+ gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ case MADDU_ACC:
+ gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ case MSUB_ACC:
+ gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ case MSUBU_ACC:
+ gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ default:
+ goto pool32axf_invalid;
+ }
+ break;
+ case 0x32:
+ switch (minor & 3) {
+ case MULT_ACC:
+ gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ case MULTU_ACC:
+ gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt);
+ break;
+ default:
+ goto pool32axf_invalid;
+ }
+ break;
case 0x2c:
switch (minor) {
case SEB:
@@ -11113,7 +11143,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
mips32_op = OPC_MSUBU;
do_mul:
check_insn(ctx, ISA_MIPS32);
- gen_muldiv(ctx, mips32_op, (ctx->opcode >> 14) & 3, rs, rt);
+ gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
default:
goto pool32axf_invalid;
@@ -11247,24 +11277,42 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
goto pool32axf_invalid;
}
break;
- case 0x35:
+ case 0x01:
switch (minor & 3) {
- case MFHI32:
+ case MFHI_ACC:
gen_HILO(ctx, OPC_MFHI, minor >> 2, rs);
break;
- case MFLO32:
+ case MFLO_ACC:
gen_HILO(ctx, OPC_MFLO, minor >> 2, rs);
break;
- case MTHI32:
+ case MTHI_ACC:
gen_HILO(ctx, OPC_MTHI, minor >> 2, rs);
break;
- case MTLO32:
+ case MTLO_ACC:
gen_HILO(ctx, OPC_MTLO, minor >> 2, rs);
break;
default:
goto pool32axf_invalid;
}
break;
+ case 0x35:
+ switch (minor) {
+ case MFHI32:
+ gen_HILO(ctx, OPC_MFHI, 0, rs);
+ break;
+ case MFLO32:
+ gen_HILO(ctx, OPC_MFLO, 0, rs);
+ break;
+ case MTHI32:
+ gen_HILO(ctx, OPC_MTHI, 0, rs);
+ break;
+ case MTLO32:
+ gen_HILO(ctx, OPC_MTLO, 0, rs);
+ break;
+ default:
+ goto pool32axf_invalid;
+ }
+ break;
default:
pool32axf_invalid:
MIPS_INVAL("pool32axf");
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